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61. 发明授权

US08084309B2 Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask 有权
标题翻译：非常薄的绝缘体上硅（ETSOI）互补金属氧化物半导体（CMOS），其具有由单个掩模形成的原位掺杂源极和漏极区域
公开(公告)号：US08084309B2
公开(公告)日：2011-12-27
申请号：US12542179
申请日：2009-08-17
申请人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/84 , H01L21/823814 , H01L21/845 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.
摘要翻译：提供一种制造电子结构的方法，其包括在衬底的SOI半导体层上形成第一导电掺杂的第一半导体材料。 SOI半导体层的厚度小于10nm。第一导电性原位掺杂的第一半导体材料从SOI半导体层的第一部分去除，其中第一导电性原位掺杂的第一半导体材料的剩余部分存在于SOI半导体层的第二部分上。第二导电性原位掺杂的第二半导体材料形成在SOI半导体层的第一部分上，其中掩模禁止在SOI半导体层的第二部分上形成第二导电性原位掺杂半导体材料。来自第一和第二导电性原位掺杂半导体材料的掺杂剂扩散到第一半导体层中以形成掺杂区域。

62. 发明申请

US20110309446A1 STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER 有权
标题翻译：具有单个间距的垂直源/源压应力的应变薄体CMOS器件
公开(公告)号：US20110309446A1
公开(公告)日：2011-12-22
申请号：US12816399
申请日：2010-06-16
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/8238 , H01L29/786 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译：一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一在图案化的栅极结构下方的半导体衬底的沟道区上。

63. 发明申请

US20110309416A1 STRUCTURE AND METHOD TO REDUCE FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：减少半导体器件中的电容的结构和方法
公开(公告)号：US20110309416A1
公开(公告)日：2011-12-22
申请号：US12819689
申请日：2010-06-21
申请人： Tenko Yamashita , Bruce B. Doris
发明人： Tenko Yamashita , Bruce B. Doris
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66484 , H01L21/764 , H01L21/823425 , H01L21/823456 , H01L29/6653 , H01L29/66628 , H01L29/7831 , H01L29/7833
摘要： A method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate that includes at a gate conductor. Forming a sacrificial material layer on at least the sidewall surfaces of the gate conductor, and forming a raised source region and a raised drain region on the semiconductor substrate, wherein the raised source region and the raised drain are separated from the gate conductor by the sacrificial material layer. The sacrificial material layer is removed to provide a void separating the gate structure from the raised source and drain regions. An encapsulating material layer is formed bridging the gate structure to each of the raised source region and the raised drain region to provide an air gap separating the gate structure from the raised source regions and the raised drain regions.
摘要翻译：提供一种形成半导体器件的方法，其包括在包括栅极导体的半导体衬底上提供栅极结构。在所述栅极导体的至少所述侧壁表面上形成牺牲材料层，以及在所述半导体衬底上形成升高的源极区域和凸起的漏极区域，其中所述凸起的源极区域和所述高的漏极通过所述牺牲层与所述栅极导体分离材料层。去除牺牲材料层以提供将栅极结构与凸起的源极和漏极区分离的空隙。形成了将栅极结构桥接到凸起源极区域和隆起漏极区域中的每一个的封装材料层，以提供将栅极结构与凸起的源极区域和升高的漏极区域分开的气隙。

64. 发明申请

US20110254080A1 TUNNEL FIELD EFFECT TRANSISTOR 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US20110254080A1
公开(公告)日：2011-10-20
申请号：US12760287
申请日：2010-04-14
申请人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Wilfried E. Haensch , Ali Khakifirooz , Isaac Lauer , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.
摘要翻译：公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。形成覆盖栅极堆叠和结的硬掩模。执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。去除硬掩模的注入部分，并露出其中一个接头。该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

65. 发明申请

US20110254015A1 METHOD FOR IMPROVING DEVICE PERFORMANCE USING EPITAXIALLY GROWN SILICON CARBON (SiC) OR SILICON-GERMANIUM (SiGe) 有权
标题翻译：使用外延硅碳化硅（SiC）或硅锗（SiGe）改善器件性能的方法
公开(公告)号：US20110254015A1
公开(公告)日：2011-10-20
申请号：US12760688
申请日：2010-04-15
申请人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir M. Shaik Adam , Balasubramanian S. Pranatharthi Haran
发明人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir M. Shaik Adam , Balasubramanian S. Pranatharthi Haran
IPC分类号： H01L29/78 , H01L21/336 , H01L29/24
CPC分类号： H01L29/66636 , H01L21/02576 , H01L21/02579 , H01L21/223 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/2807 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7848
摘要： A semiconductor substrate including a field effect transistor (FET) and a method of producing the same wherein a stressor is provided in a recess before the source/drain region is formed. The device has an increased carrier mobility in the channel region adjacent to the gate electrode.
摘要翻译：包括场效应晶体管（FET）的半导体衬底及其制造方法，其中在形成源极/漏极区域之前的凹部中设置应力器。器件在与栅电极相邻的沟道区域中具有增加的载流子迁移率。

66. 发明授权

US08035173B2 CMOS transistors with differential oxygen content high-K dielectrics 有权
标题翻译：具有差异氧含量高K电介质的CMOS晶体管
公开(公告)号：US08035173B2
公开(公告)日：2011-10-11
申请号：US12712371
申请日：2010-02-25
申请人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Huiming Bu , Eduard A. Cartier , Bruce B. Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L29/78
CPC分类号： H01L21/823864 , H01L21/823814 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/4908 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.
摘要翻译：在半导体衬底上形成包含第一高k电介质部分的NFET和包含第二高k栅极电介质部分的PFET。栅极侧壁氮化物形成在NFET的栅极上，而PFET的侧壁保持没有栅极侧壁氮化物。直接在PFET栅极堆叠的侧壁上和NFET上的栅极侧壁氮化物上形成氧化物间隔物。在高温处理之后，第一和第二介质部分含有非化学计量的缺氧高k电介质材料。半导体结构在氧气环境中进行退火，在该环境中，氧气通过氧化物间隔物扩散到第二高k电介质部分。 PFET包括更高化学计量的高k电介质材料，并且NFET包含较少化学计量的高k电介质材料。本发明优化了PFET和NFET的阈值电压。

67. 发明申请

US20110227165A1 HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE 有权
公开(公告)号：US20110227165A1
公开(公告)日：2011-09-22
申请号：US13151525
申请日：2011-06-02
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ali Khakifirooz
IPC分类号： H01L27/092
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/1054 , H01L29/66795
摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

68. 发明授权

US08022488B2 High-performance FETs with embedded stressors 有权
标题翻译：具有嵌入式应力的高性能FET
公开(公告)号：US08022488B2
公开(公告)日：2011-09-20
申请号：US12566004
申请日：2009-09-24
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/02
CPC分类号： H01L29/7848 , H01L21/2257 , H01L21/26586 , H01L29/165 , H01L29/41775 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.
摘要翻译：提供了高性能半导体结构和制造这种结构的方法。半导体结构包括位于半导体衬底的上表面上的至少一个栅堆叠，例如FET。该结构还包括在至少一个栅极堆叠的沟道上引起应变的第一外延半导体材料。第一外延半导体材料位于至少一个栅极堆叠的基准面上，基本上位于衬底中的存在于至少一个栅极堆叠的相对侧上的一对凹陷区域内。扩散扩展区域位于每个凹陷区域中的所述第一外延半导体材料的上表面内。该结构还包括位于扩散扩展区的上表面上的第二外延半导体材料。第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

69. 发明授权

US08003455B2 Implantation using a hardmask 有权
标题翻译：使用硬掩模进行植入
公开(公告)号：US08003455B2
公开(公告)日：2011-08-23
申请号：US12469710
申请日：2009-05-21
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L21/266 , H01L21/823892
摘要： A method for processing CMOS wells, and performing multiple ion implantations with the use of a single hard mask is disclosed. The method includes forming and patterning a hardmask over a substrate, whereby the hardmask attains a first opening. The substrate may be a semiconductor substrate. The method further includes performing a first ion implantation, during which, outside the first opening the hardmask is essentially preventing ions from reaching the substrate. The method further involves the application of a photoresist in such a manner that the photoresist is covering the hardmask, and it is also filling up the first opening. This is followed by using the photoresist to pattern the hardmask, whereby the hardmask attains a second opening. The method further includes performing a second ion implantation, during which, outside the second opening, the hardmask and the photoresist, which fills the first opening, are essentially preventing ions from reaching the substrate. The two ion implantations may be used to form the two type of CMOS wells.
摘要翻译：公开了一种用于处理CMOS阱的方法，并且使用单个硬掩模执行多个离子注入。该方法包括在基板上形成和图案化硬掩模，由此硬掩模获得第一开口。衬底可以是半导体衬底。该方法还包括执行第一离子注入，其间在第一开口外部，硬掩模基本上防止离子到达衬底。该方法还涉及以光致抗蚀剂覆盖硬掩模的方式施加光致抗蚀剂，并且其还填充第一开口。然后使用光致抗蚀剂来模拟硬掩模，由此硬掩模获得第二开口。该方法还包括执行第二离子注入，其间在第二开口外部，填充第一开口的硬掩模和光致抗蚀剂基本上防止离子到达衬底。两个离子注入可用于形成两种类型的CMOS阱。

70. 发明授权

US07999323B2 Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices 有权
标题翻译：使用金属/金属氮化物双层作为自对准积极缩放的CMOS器件中的栅电极
公开(公告)号：US07999323B2
公开(公告)日：2011-08-16
申请号：US12542087
申请日：2009-08-17
申请人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
发明人： Eduard A. Cartier , Matthew W. Copel , Bruce B. Doris , Rajarao Jammy , Young-Hee Kim , Barry P. Linder , Vijay Narayanan , Vamsi K. Paruchuri , Keith Kwong Hon Wong
IPC分类号： H01L29/00
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
摘要翻译：本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。本发明还提供了制造这种CMOS结构的方法。

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