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61. 发明授权

US06400036B1 Flip-chip package structure and method of fabricating the same 有权
标题翻译：倒装芯片封装结构及其制造方法
公开(公告)号：US06400036B1
公开(公告)日：2002-06-04
申请号：US09920069
申请日：2001-08-01
申请人： Wei-Sen Tang , Han-Ping Pu
发明人： Wei-Sen Tang , Han-Ping Pu
IPC分类号： H01L2144
CPC分类号： H01L24/32 , H01L21/563 , H01L24/28 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/26145 , H01L2224/26175 , H01L2224/27013 , H01L2224/32145 , H01L2224/73203 , H01L2224/73204 , H01L2224/83051 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/351 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A flip-chip package technology is proposed for use to fabricate a dual-chip integrated circuit package that includes two semiconductor chips in a single package unit, which is characterized in the forming of a flash-barrier structure that can help prevent the underfill material used in flip-chip underfill process from flashing to other unintended areas. The flash-barrier structure can be either a protruded dam structure over the underlying semiconductor chip, or a groove in a coating layer formed over the underlying semiconductor chip. During flip-chip underfill process, the flash-barrier structure can confine the underfill material within the intended area and prevent the underfill material from flowing to other unintended areas such as nearby bonding pads, so that the finished package product can be assured in quality and reliability.
摘要翻译：提出了一种倒装芯片封装技术，用于制造双芯片集成电路封装，其包括在单个封装单元中的两个半导体芯片，其特征在于形成闪光屏障结构，其可以帮助防止使用的底部填充材料在从闪烁到其他非预期区域的倒装芯片底部填充过程中。闪光屏障结构可以是下面的半导体芯片上的突出的坝结构，也可以是形成在下面的半导体芯片上的涂层中的凹槽。在倒装芯片底部填充过程中，闪光屏障结构可以将底部填充材料限制在预期区域内，并防止底部填充材料流到其他非预期区域（例如附近的焊盘），从而可以确保成品包装产品的质量和可靠性。

62. 发明授权

US09159686B2 Crack stopper on under-bump metallization layer 有权
标题翻译：在凸块下金属化层上的裂纹塞
公开(公告)号：US09159686B2
公开(公告)日：2015-10-13
申请号：US13443556
申请日：2012-04-10
申请人： Yu-Feng Chen , Chun-Hung Lin , Han-Ping Pu , Chih-Hang Tung , Kai-Chiang Wu , Ming-Che Ho
发明人： Yu-Feng Chen , Chun-Hung Lin , Han-Ping Pu , Chih-Hang Tung , Kai-Chiang Wu , Ming-Che Ho
IPC分类号： H01L23/00 , H01L23/488
CPC分类号： H01L24/13 , H01L23/488 , H01L24/02 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/16 , H01L2224/0401 , H01L2224/05027 , H01L2224/05111 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05551 , H01L2224/05555 , H01L2224/05572 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10125 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13012 , H01L2224/13076 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16237 , H01L2224/16238 , H01L2224/81191 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2924/00012 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor die includes a crack stopper on an under-bump metallization (UBM) layer. The crack stopper is in the shape of hollow cylinder with at least two openings.
摘要翻译：半导体管芯包括在凸块下金属化（UBM）层上的裂纹阻挡层。裂缝止动器为具有至少两个开口的中空圆筒形状。

63. 发明授权

US09064881B2 Protecting flip-chip package using pre-applied fillet 有权
标题翻译：使用预应用的圆角保护倒装芯片封装
公开(公告)号：US09064881B2
公开(公告)日：2015-06-23
申请号：US12944453
申请日：2010-11-11
申请人： Tsung-Fu Tsai , Yian-Liang Kuo , Ming-Song Sheu , Yu-Ling Tsai , Chen-Shien Chen , Han-Ping Pu
发明人： Tsung-Fu Tsai , Yian-Liang Kuo , Ming-Song Sheu , Yu-Ling Tsai , Chen-Shien Chen , Han-Ping Pu
IPC分类号： H01L23/29 , H01L21/56 , H01L23/00
CPC分类号： H01L21/78 , H01L21/02013 , H01L21/02016 , H01L21/563 , H01L23/295 , H01L23/562 , H01L24/32 , H01L24/743 , H01L24/81 , H01L2224/16225 , H01L2224/26145 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/81009 , H01L2224/81191 , H01L2224/83104 , H01L2224/83192 , H01L2224/92125 , H01L2924/10156 , H01L2924/14 , H01L2924/00012 , H01L2924/10155 , H01L2924/00
摘要： A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.
摘要翻译：模具具有第一表面，与第一表面相对的第二表面，并且侧壁包括第一部分和第二部分，其中第一部分比第二部分更靠近第一表面。圆角接触模具的侧壁的第一部分并且环绕模具。工件通过焊料凸块与模具结合，第二表面面向工件。第一底部填充物填充模具和工件之间的间隙，其中第一底部填充物接触圆角，并且其中第一底部填充物和圆角由不同的材料形成。

64. 发明授权

US08970033B2 Extending metal traces in bump-on-trace structures 有权
标题翻译：在痕迹结构中扩展金属痕迹
公开(公告)号：US08970033B2
公开(公告)日：2015-03-03
申请号：US13035586
申请日：2011-02-25
申请人： Yu-Feng Chen , Yuh Chern Shieh , Tsung-Shu Lin , Han-Ping Pu , Jiun Yi Wu , Tin-Hao Kuo
发明人： Yu-Feng Chen , Yuh Chern Shieh , Tsung-Shu Lin , Han-Ping Pu , Jiun Yi Wu , Tin-Hao Kuo
IPC分类号： H01L23/498 , H01L23/00
CPC分类号： H01L24/16 , H01L23/49816 , H01L23/49838 , H01L24/13 , H01L24/17 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16013 , H01L2224/16225 , H01L2224/16227 , H01L2924/00013 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/00014 , H01L2924/00 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.
摘要翻译：一种装置包括工件和工件表面上的金属迹线。在工件的表面形成凸起跟踪（BOT）。 BOT结构包括金属凸块和将金属凸块接合到金属迹线的一部分的焊料凸块。金属迹线包括未被焊料凸块覆盖的金属迹线延伸。

65. 发明授权

US08927333B2 Die carrier for package on package assembly 有权
标题翻译：封装组件上的封装的载体
公开(公告)号：US08927333B2
公开(公告)日：2015-01-06
申请号：US13302059
申请日：2011-11-22
申请人： Tsung-Shu Lin , Yu-Ling Tsai , Han-Ping Pu
发明人： Tsung-Shu Lin , Yu-Ling Tsai , Han-Ping Pu
IPC分类号： H01L21/00 , H01L21/76 , H01L23/48 , H01L23/552 , H01L25/10
CPC分类号： H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/1017 , H01L2225/1041 , H01L2225/1058 , H01L2924/00012
摘要： A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.
摘要翻译：提供了一种用于在回流操作期间维持管芯对准的封装封装布置。第一顶模具有焊料凸块的第一布置。底部封装具有电连接到第一焊料凸点布置的第一电气布置。模具载体具有限定在其底表面上的多个安装区域，其中第一顶模在多个安装区域中的第一个处粘附到模具载体。具有第二排列焊料凸点的第二顶模和虚模具之一也在模具载体的多个安装区域的第二位置处固定到模具载体。焊料凸块的第一和第二布置彼此对称，其中在回流操作期间平衡表面张力，并且通常相对于底部封装固定模具载体的取向。

66. 发明授权

US08759964B2 Wafer level package structure and fabrication methods 有权
标题翻译：晶圆级封装结构及制作方法
公开(公告)号：US08759964B2
公开(公告)日：2014-06-24
申请号：US11779192
申请日：2007-07-17
申请人： Han-Ping Pu , Mirng-Ji Lii
发明人： Han-Ping Pu , Mirng-Ji Lii
IPC分类号： H01L21/00
CPC分类号： H01L21/568 , H01L21/561 , H01L21/6835 , H01L23/3107 , H01L24/13 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2224/20 , H01L2224/97 , H01L2924/00013 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/82 , H01L2224/29099 , H01L2924/00
摘要： A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.
摘要翻译：提供一种形成具有对半导体管芯的损伤减小的封装结构的方法。所述方法包括提供在所述管芯的顶表面上包括接合焊盘的管芯; 在所述模具的接合焊盘上形成凸起，其中所述凸起具有高于所述模具的顶表面的顶表面; 将所述管芯安装在芯片载体上，其中所述凸块附接到所述芯片载体上; 用模塑料将模具成型到芯片载体上; 将芯片载体从芯片上拆下; 以及在模具的凸起上形成并电连接到模具的凸块上的再分布迹线。

67. 发明申请

US20130119532A1 Bumps for Chip Scale Packaging 审中-公开
标题翻译：用于芯片尺寸包装的冲击
公开(公告)号：US20130119532A1
公开(公告)日：2013-05-16
申请号：US13294859
申请日：2011-11-11
申请人： Chun-Hung Lin , Yu-Feng Chen , Tsung-Shu Lin , Han-Ping Pu , Hsien-Wei Chen
发明人： Chun-Hung Lin , Yu-Feng Chen , Tsung-Shu Lin , Han-Ping Pu , Hsien-Wei Chen
IPC分类号： H01L23/485
CPC分类号： H01L24/14 , H01L23/3114 , H01L23/3171 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0233 , H01L2224/02331 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/03462 , H01L2224/0401 , H01L2224/05018 , H01L2224/05024 , H01L2224/0508 , H01L2224/05085 , H01L2224/05558 , H01L2224/05569 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06135 , H01L2224/06136 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/1403 , H01L2224/14131 , H01L2224/14135 , H01L2224/14136 , H01L2224/14179 , H01L2224/16225 , H01L2224/17051 , H01L2224/81191 , H01L2224/81815 , H01L2924/00 , H01L2924/00014 , H01L2924/351 , H01L2924/3512 , H01L2924/00012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2224/05552
摘要： A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.
摘要翻译：芯片级半导体器件包括半导体管芯，第一突起和第二突起。具有第一直径和第一高度的第一凸块形成在半导体管芯的外部区域上。具有第二直径和第二高度的第二凸起形成在半导体管芯的内部区域上。第二直径大于第一直径，而第二高度与第一高度相同。通过改变凸块的形状，应力和应变可通过凸块重新分布。结果，提高了芯片级半导体器件的热循环可靠性。

68. 发明授权

US08373282B2 Wafer level chip scale package with reduced stress on solder balls 有权
标题翻译：晶圆级芯片级封装，焊球应力减小
公开(公告)号：US08373282B2
公开(公告)日：2013-02-12
申请号：US13162394
申请日：2011-06-16
申请人： Yu-Feng Chen , Yu-Ling Tsai , Han-Ping Pu , Hung-Jui Kuo , Yu Yi Huang
发明人： Yu-Feng Chen , Yu-Ling Tsai , Han-Ping Pu , Hung-Jui Kuo , Yu Yi Huang
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/562 , H01L23/293 , H01L23/3114 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05569 , H01L2224/05572 , H01L2224/131 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
摘要： A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.
摘要翻译：一种结构包括半导体衬底上的金属焊盘，具有金属焊盘上方的一部分的钝化层以及钝化层上的第一聚酰亚胺层，其中第一聚酰亚胺层具有第一厚度和第一杨氏模量。后钝化互连（PPI）包括在第一聚酰亚胺层之上的第一部分，以及延伸到钝化层和第一聚酰亚胺层中的第二部分。 PPI电耦合到金属垫。第二个聚酰亚胺层位于PPI之上。第二聚酰亚胺层具有第二厚度和第二杨氏模量。厚度比和杨氏模量比中的至少一个大于1.0，其中厚度比是第一厚度与第二厚度的比率，杨氏模量比是第二杨氏模量与第一杨氏模量之比模数。

69. 发明授权

US07888236B2 Semiconductor device and fabrication methods thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07888236B2
公开(公告)日：2011-02-15
申请号：US11798432
申请日：2007-05-14
申请人： Han-Ping Pu , Bai-Yao Lou , Dean Wang , Ching-Wen Hsiao , Kai-Ming Ching , Chen-Cheng Kuo , Wen-Chih Chiou , Ding-Chung Lu , Shang-Yun Hou
发明人： Han-Ping Pu , Bai-Yao Lou , Dean Wang , Ching-Wen Hsiao , Kai-Ming Ching , Chen-Cheng Kuo , Wen-Chih Chiou , Ding-Chung Lu , Shang-Yun Hou
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L2224/05001 , H01L2224/05022 , H01L2224/05023 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/11 , H01L2924/00014
摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.
摘要翻译：一种封装半导体器件的方法。提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。沿着划线区域锯切基板，通过开口。在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。图案化第一结构层以在第一划线区域内形成第一开口。提供了包括分别由第二划线区域分开的多个第二裸片的第二衬底，其中至少一个第二结构层覆盖在衬底上。图案化第二结构层以在第二划线区域内形成第二开口。第一基板和第二基板被接合以形成堆叠结构。沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。

70. 发明授权

US07750467B2 Chip scale package structure with metal pads exposed from an encapsulant 有权
标题翻译：具有从密封剂暴露的金属焊盘的芯片级封装结构
公开(公告)号：US07750467B2
公开(公告)日：2010-07-06
申请号：US11891134
申请日：2007-08-08
申请人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L23/485
CPC分类号： H01L21/561 , H01L21/568 , H01L23/3114 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/20 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.
摘要翻译：公开了一种芯片级封装结构及其制造方法。该方法包括在载体的预定部分上形成金属垫; 在载体上安装芯片，每个芯片具有焊接到金属焊盘的多个导电凸块; 在载体上形成密封剂以封装芯片和导电凸块; 移除载体以暴露金属垫和甚至具有密封剂表面的金属垫; 在所述密封剂上形成电连接到所述金属焊盘的多个第一导电迹线; 在所述第一导电迹线上施加焊接掩模，以及在所述焊接掩模上形成多个开口以暴露所述第一导电迹线的预定部分; 在所述预定部分上形成多个导电元件; 以及切割所述密封剂以形成多个芯片级封装结构。

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