专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US5674770A Method of fabricating an SRAM device with a self-aligned thin film transistor structure 失效
标题翻译：制造具有自对准薄膜晶体管结构的SRAM器件的方法
公开(公告)号：US5674770A
公开(公告)日：1997-10-07
申请号：US721664
申请日：1996-09-27
申请人： Jin-Yuan Lee , Shou-Gwo Wuu
发明人： Jin-Yuan Lee , Shou-Gwo Wuu
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： A process for fabricating SRAM cells, including MOSFET devices, as well as thin film transistor structures, has been developed. The process features self-alignment of the MOSFET polysilicon gate structure to the polysilicon gate structure of the thin film transistor. Self-alignment is accomplished via a photolithographic and dry etching patterning procedure, applied to a combination of polysilicon, and insulator layers, resulting in the desired polysilicon gate structures for both the MOSFET and thin film transistor devices.
摘要翻译：已经开发了用于制造包括MOSFET器件以及薄膜晶体管结构的SRAM单元的工艺。该工艺将MOSFET多晶硅栅极结构的自对准特性与薄膜晶体管的多晶硅栅极结构相结合。通过光刻和干蚀刻图案化程序实现自对准，施加到多晶硅和绝缘体层的组合，导致用于MOSFET和薄膜晶体管器件的期望的多晶硅栅极结构。

62. 发明授权

US08994082B2 Transistors, methods of manufacturing thereof, and image sensor circuits with reduced RTS noise 有权
标题翻译：晶体管，其制造方法和具有减少的RTS噪声的图像传感器电路
公开(公告)号：US08994082B2
公开(公告)日：2015-03-31
申请号：US13250856
申请日：2011-09-30
申请人： Feng-Chi Hung , Jhy-Jyi Sze , Shou-Gwo Wuu
发明人： Feng-Chi Hung , Jhy-Jyi Sze , Shou-Gwo Wuu
IPC分类号： H01L31/062 , H01L31/113 , H01L21/265 , H01L29/78 , H01L27/146 , H01L21/28
CPC分类号： H01L27/14616 , H01L21/0223 , H01L21/26506 , H01L21/26586 , H01L21/266 , H01L21/28123 , H01L21/2822 , H01L21/76224 , H01L27/14603 , H01L27/14612 , H01L27/1463 , H01L29/0653 , H01L29/41775 , H01L29/42368 , H01L29/66568 , H01L29/78
摘要： Transistors, methods of manufacturing thereof, and image sensor circuits with reduced random telegraph signal (RTS) noise are disclosed. In one embodiment, a transistor includes a channel disposed between two isolation regions in a workpiece. The channel has edge regions proximate the isolation regions and a central region between the edge regions. The transistor includes a gate dielectric disposed over the channel, and a gate disposed over the gate dielectric. The transistor includes a voltage threshold modification feature proximate the edge regions configured to increase a voltage threshold of the transistor proximate edge regions relative to the central region of the channel.
摘要翻译：公开了晶体管，其制造方法和具有减少的随机电报信号（RTS）噪声的图像传感器电路。在一个实施例中，晶体管包括设置在工件中的两个隔离区域之间的通道。通道具有靠近隔离区域的边缘区域和边缘区域之间的中心区域。晶体管包括设置在通道上方的栅极电介质和设置在栅极电介质上的栅极。晶体管包括靠近边缘区域的电压阈值修改特征，其被配置成相对于通道的中心区域增加晶体管的边缘区域的电压阈值。

63. 发明授权

US08558351B2 Alignment for backside illumination sensor 有权
标题翻译：背面照明传感器对准
公开(公告)号：US08558351B2
公开(公告)日：2013-10-15
申请号：US13550140
申请日：2012-07-16
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/71 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.
摘要翻译：提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

64. 发明申请

US20120280351A1 ALIGNMENT FOR BACKSIDE ILLUMINATION SENSOR 有权
标题翻译：背面照明传感器对准
公开(公告)号：US20120280351A1
公开(公告)日：2012-11-08
申请号：US13550140
申请日：2012-07-16
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L23/544 , H01L27/146
CPC分类号： H01L23/544 , H01L21/71 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.
摘要翻译：提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

65. 发明授权

US08227899B2 Alignment for backside illumination sensor 有权
标题翻译：背面照明传感器对准
公开(公告)号：US08227899B2
公开(公告)日：2012-07-24
申请号：US12553586
申请日：2009-09-03
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/71 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.
摘要翻译：提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

66. 发明授权

US08216905B2 Stress engineering to reduce dark current of CMOS image sensors 有权
标题翻译：应力工程可以减少CMOS图像传感器的暗电流
公开(公告)号：US08216905B2
公开(公告)日：2012-07-10
申请号：US12768063
申请日：2010-04-27
申请人： Ru-Shang Hsiao , Nai-Wen Cheng , Chung-Te Lin , Chien-Hsien Tseng , Shou-Gwo Wuu
发明人： Ru-Shang Hsiao , Nai-Wen Cheng , Chung-Te Lin , Chien-Hsien Tseng , Shou-Gwo Wuu
IPC分类号： H01L21/336
CPC分类号： H01L27/1463 , H01L21/324 , H01L21/823878 , H01L22/34 , H01L27/14689 , H01L29/7842
摘要： The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.
摘要翻译：上述有源像素单元结构和制备这种结构的方法能够减少有源像素单元的暗电流和白细胞计数。制备有源像素单元结构的过程在衬底上引入应力，这可能导致有源像素单元的暗电流和白细胞计数增加。通过沉积应力层作为预金属介电层的一部分，其应力引起应力，暗电流和白细胞计数都可以减小。如果有源像素单元的晶体管是NMOS，则载流子迁移率也可以通过拉伸应力层增加。拉曼光谱可用于测量在沉积应力层之前施加在基底上的应力。

67. 发明授权

US07649231B2 Asymmetrical reset transistor with double-diffused source for CMOS image sensor 有权
标题翻译： CMOS图像传感器双扩散源非对称复位晶体管
公开(公告)号：US07649231B2
公开(公告)日：2010-01-19
申请号：US10682269
申请日：2003-10-09
申请人： Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Chien-Hsien Tseng
发明人： Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Chien-Hsien Tseng
IPC分类号： H01L23/62
CPC分类号： H01L27/14689 , H01L27/0802 , H01L27/14609 , H01L27/1463
摘要： A new method to form CMOS image sensors in the manufacture of an integrated circuit device is achieved. The method comprises providing a semiconductor substrate. Sensor diodes are formed in the semiconductor substrate each comprising a first terminal and a second terminal. Gates are formed for transistors in the CMOS image sensors. The gates comprise a conductor layer overlying the semiconductor substrate with an insulating layer therebetween. The transistors include reset transistors. Ions are implanted into the semiconductor substrate to form source/drain regions for the transistors. The source regions of the reset transistors are formed in the first terminals of the sensor diodes. Ions are implanted into the reset transistor sources to form double diffused sources. The implanting is blocked from other source/drain regions.
摘要翻译：实现了在制造集成电路器件中形成CMOS图像传感器的新方法。该方法包括提供半导体衬底。传感器二极管形成在每个包括第一端子和第二端子的半导体衬底中。为CMOS图像传感器中的晶体管形成栅极。栅极包括覆盖半导体衬底的导体层，其间具有绝缘层。晶体管包括复位晶体管。将离子注入到半导体衬底中以形成用于晶体管的源极/漏极区域。复位晶体管的源极区域形成在传感器二极管的第一端子中。离子被植入到复位晶体管源中以形成双扩散源。植入物从其它源极/漏极区域被阻挡。

68. 发明申请

US20090189233A1 CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译： CMOS图像传感器及其制造方法
公开(公告)号：US20090189233A1
公开(公告)日：2009-07-30
申请号：US12020149
申请日：2008-01-25
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu , Chi-Hsin Lo , Feng-Jia Shiu , Chung-Yi Yu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu , Chi-Hsin Lo , Feng-Jia Shiu , Chung-Yi Yu
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14625 , H01L27/14627 , H01L27/14636 , H01L27/14685
摘要： An optical image sensor is fabricated by forming a pixel array and a peripheral region surrounding the pixel array on a semiconductor substrate, the peripheral region containing peripheral circuitry. An inter-level-dielectric layer is formed over the substrate and a plurality of interconnect wiring layers are formed over the inter-level-dielectric layer. Each interconnect wiring layer includes interconnecting metal features and a layer of inter-level-dielectric material covering the interconnecting metal features. The plurality of interconnect wiring layers are provided in a manner that there are N levels of wiring layers in the peripheral region and 1 to (N−1) levels of wiring layers over the pixel array. An etch-stop layer is formed over the top-most level interconnecting metal features in the peripheral region.
摘要翻译：通过在半导体衬底上形成围绕像素阵列的像素阵列和外围区域来制造光学图像传感器，该外围区域包含外围电路。层间电介质层形成在衬底之上，并且在层间电介质层之上形成多个互连布线层。每个互连布线层包括互连金属特征和覆盖互连金属特征的层间电介质材料层。多个互连布线层的设置方式是在像素阵列的周边区域中有N层布线层和布线层的1层（N-1）层。在外围区域中最顶层的互连金属特征上形成蚀刻停止层。

69. 发明授权

US07553689B2 Semiconductor device with micro-lens and method of making the same 有权
标题翻译：具有微透镜的半导体器件及其制造方法
公开(公告)号：US07553689B2
公开(公告)日：2009-06-30
申请号：US11181189
申请日：2005-07-13
申请人： Jeng-Shyan Lin , Chien-Hsien Tseng , Shou-Gwo Wuu , Ho-Ching Chien , Dun-Nian Yaung , Hung-Jen Hsu
发明人： Jeng-Shyan Lin , Chien-Hsien Tseng , Shou-Gwo Wuu , Ho-Ching Chien , Dun-Nian Yaung , Hung-Jen Hsu
IPC分类号： H01L21/00
CPC分类号： H01L27/14685 , H01L27/14623 , H01L27/14627 , H01L27/14632
摘要： A semiconductor device including a semiconductor substrate having a photosensor formed therein; a first layer overlying the substrate, the first layer includes a portion having a generally concave shaped surface being the negative shaped of a micro-lens to be formed there over; a second layer overlying the first layer, the second layer including a generally convex shaped portion vertically aligned with and mating with the generally concave shaped surface, the generally convex shaped portion being constructed and arranged to define a micro-lens positioned to cause parallel light passing through the micro-lens to converge on and strike the photosensor.
摘要翻译：一种半导体器件，包括其中形成有光电传感器的半导体衬底; 覆盖衬底的第一层，第一层包括具有大致凹形形状的表面的部分，其为在其上形成的微透镜的负形状; 覆盖第一层的第二层，第二层包括垂直对准并与大致凹形的表面配合的大致凸形的部分，大体上凸形的部分被构造和布置以限定微透镜，定位成使得平行光通过通过微透镜收敛并撞击光电传感器。

70. 发明授权

US07507596B2 Method of fabricating a high quantum efficiency photodiode 有权
标题翻译：制造高量子效率光电二极管的方法
公开(公告)号：US07507596B2
公开(公告)日：2009-03-24
申请号：US11360750
申请日：2006-02-23
申请人： Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chen , Chien-Hsien Tseng , Jeng-Shyan Lin
发明人： Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chen , Chien-Hsien Tseng , Jeng-Shyan Lin
IPC分类号： H01L21/00
CPC分类号： H01L31/103 , H01L27/1463 , H01L27/14632 , H01L27/14643 , H01L31/02161
摘要： The present invention is CMOS image sensor and its method of fabrication. This invention provides an efficient structure to improve the quantum efficiency of a CMOS image sensor with borderless contact. The image sensor comprises a N-well/P-substrate type photodiode with borderless contact and dielectric structure covering the photodiode region. The dielectric structure is located between the photodiode and the interlevel dielectric (ILD) and is used as a buffer layer for the borderless contact. The method of fabricating a high performance photodiode comprises forming a photodiode in the n-well region of a shallow trench, and embedding a dielectric material between the ILD oxide and the photodiode having a refraction index higher than the ILD oxide.
摘要翻译：本发明是CMOS图像传感器及其制造方法。本发明提供了一种提高无边界接触CMOS图像传感器的量子效率的有效结构。图像传感器包括覆盖光电二极管区域的无接触接触和介电结构的N阱/ P基板型光电二极管。电介质结构位于光电二极管和层间电介质（ILD）之间，用作无边界接触的缓冲层。制造高性能光电二极管的方法包括在浅沟槽的n阱区域中形成光电二极管，并且在ILD氧化物和具有高于ILD氧化物的折射率的光电二极管之间嵌入电介质材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式