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61. 发明授权

US5182811A Exception, interrupt, and trap handling apparatus which fetches addressing and context data using a single instruction following an interrupt 失效
标题翻译：异常，中断和陷阱处理设备，使用中断之后的单个指令获取寻址和上下文数据
公开(公告)号：US5182811A
公开(公告)日：1993-01-26
申请号：US554945
申请日：1990-07-10
申请人： Ken Sakamura
发明人： Ken Sakamura
IPC分类号： G06F9/48 , G06F13/24
CPC分类号： G06F9/4812 , G06F13/24
摘要： A data processor executes the exception process, interrupt process and the trap instruction of internal interrupt instructions in a unified manner. The data processor is adapted to read an internal state variable simultaneously with reading the head address of an EIT process handler from an external memory when an EIT process is started so that it enables the internal state to be set on the basis of the information of the variable when the EIT process handler starts. The data processor is provided with multiple EIT process means which, when a plurality of EIT process requests are generated, decides the process order on the basis of priority from the content of the request. The data processor is also provided with means which specially treats the EIT process acceptance condition after returning from one EIT process handler, and thereby is generously free in programming.
摘要翻译：数据处理器以统一的方式执行异常处理，中断处理和内部中断指令的陷阱指令。数据处理器适于在EIT处理开始时从外部存储器读取EIT处理处理程序的头地址同时读取内部状态变量，使得其能够基于内部状态变量的信息来设置内部状态变量当EIT进程处理程序启动时变量。数据处理器具有多个EIT处理装置，当产生多个EIT处理请求时，根据请求的内容基于优先级来决定处理顺序。数据处理器还提供了从一个EIT处理处理程序返回后特别处理EIT过程接受条件的手段，从而在编程中慷慨。

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