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61. 发明授权

US06996377B1 PLL circuit and radio communication terminal apparatus using the same 失效
公开(公告)号：US06996377B1
公开(公告)日：2006-02-07
申请号：US09787380
申请日：1999-09-14
申请人： Taizo Yamawaki , Takefumi Endo , Kazuo Watanabe , Kazuaki Hori , Julian Hildersley
发明人： Taizo Yamawaki , Takefumi Endo , Kazuo Watanabe , Kazuaki Hori , Julian Hildersley
IPC分类号： H04B1/40
CPC分类号： H03L7/10 , H03D13/007 , H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/12 , H04B1/406
摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.

62. 发明申请

US20060015791A1 Decoding method, decoding device, program, recording/reproduction device and method, and reproduction device and method 失效
标题翻译：解码方法，解码装置，程序，记录/再现装置和方法以及再现装置和方法
公开(公告)号：US20060015791A1
公开(公告)日：2006-01-19
申请号：US10523452
申请日：2004-05-28
申请人： Atsushi Kikuchi , Masayuki Hattori , Toshiyuki Miyauchi , Kazuo Watanabe , Makiko Kan
发明人： Atsushi Kikuchi , Masayuki Hattori , Toshiyuki Miyauchi , Kazuo Watanabe , Makiko Kan
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , G11B20/18 , G11B20/1866 , G11B2020/1836 , H03M13/1111 , H03M13/1191 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2936
摘要： The present invention relates to a decoding method and a decoder, a program, a recording-and-reproducing apparatus and a method, and a reproducing apparatus and a method that are suitable for decoding encoded data encoded by using a linear code on ring R. A low-density processing unit performs parity-check-matrix low-density processing, performs linear combination for rows of a parity check matrix included in an obtained reception word, and generates a parity check matrix according to the linear-combination result, thereby reducing the density of the parity check matrix used for decoding, at step S21. Then, at step S22, an LDPC decoding unit performs decoding by using a sum product algorithm (SPA) by using the parity check matrix whose density is reduced through the processing performed at step S21. Where the processing at step S22 is finished, the LDPC decoding unit finishes decoding for the reception word. The present invention can be used for an error-correction system.
摘要翻译：本发明涉及适用于对通过使用环R上的线性码编码的编码数据进行解码的解码方法和解码器，程序，记录和再现装置和方法以及再现装置和方法。低密度处理单元执行奇偶校验矩阵低密度处理，对获得的接收字中包含的奇偶校验矩阵的行进行线性组合，并根据线性组合结果生成奇偶校验矩阵，从而减少在步骤S21中用于解码的奇偶校验矩阵的密度。然后，在步骤S22，LDPC解码单元通过使用通过使用密度减小的奇偶校验矩阵的和乘积算法（SPA）来执行解码在步骤S2执行的处理。在步骤S22的处理完成的情况下，LDPC解码单元完成接收字的解码。本发明可以用于纠错系统。

63. 发明授权

US06608781B1 Nonvolatile semiconductor memory device applying positive source and substrate voltages during a programming period 有权
标题翻译：在编程期间施加正的源极和衬底电压的非易失性半导体存储器件
公开(公告)号：US06608781B1
公开(公告)日：2003-08-19
申请号：US09650158
申请日：2000-08-28
申请人： Toshikatsu Jinbo , Kazuo Watanabe
发明人： Toshikatsu Jinbo , Kazuo Watanabe
IPC分类号： G11C700
CPC分类号： G11C16/30 , G11C16/0416 , G11C16/10
摘要： According to the present invention, a voltage of 10.5 V, a voltage of 6.5 V and a voltage of 0.5 V are respectively applied to the control gate, the drain and the source of a memory cell that is a programming target. And a voltage of 0 V (a ground voltage) is applied to the control gate of a memory cell that is not a programming target and that does not belong to the row in which of the programming target memory cell is located. As a result, it is ensured that the memory cell that is not the programming target is non-conductive, and that the drain-substrate electrical field of the memory cell that is the programming target is reduced.
摘要翻译：根据本发明，作为编程对象的存储单元的控制栅极，漏极和源极分别施加10.5V的电压，6.5V的电压和0.5V的电压。并且将不是编程对象的不属于编程对象存储单元的行的存储单元的控制栅极施加0V的电压（接地电压）。结果，确保不是编程对象的存储单元是非导通的，并且减小作为编程对象的存储单元的漏极 - 基板电场。

64. 发明授权

US06388684B1 Method and apparatus for displaying a target region and an enlarged image 失效
标题翻译：用于显示目标区域和放大图像的方法和装置
公开(公告)号：US06388684B1
公开(公告)日：2002-05-14
申请号：US08058199
申请日：1993-06-25
申请人： Kazuaki Iwamura , Yasuyuki Kikuchi , Kazuo Watanabe , Masakazu Matsuo , Yoshizo Ito
发明人： Kazuaki Iwamura , Yasuyuki Kikuchi , Kazuo Watanabe , Masakazu Matsuo , Yoshizo Ito
IPC分类号： G06F314
CPC分类号： G09B29/106
摘要： An image displaying method and apparatus for simultaneously displaying an enlargement target of an entire original image and its enlarged image on a display screen by automatically disposing the enlarged image. The image displaying apparatus includes display for displaying an enlarged image of part of the entire original image including characters, patterns, etc. in a relation superposed on the entire original image, input apparatus for pointing to specify the enlargement target in the entire original image, and automatic disposing apparatus for preferentially specifying and computing the values of the area of the enlargement target region, the area of the enlarged image display region and the enlargement ratio so as to maximize one of these values and disposing the enlarged image on the basis of the result of computation. Further, in order that the enlarged image is easily visible, the enlargement target region and the enlarged image display region are disposed and displayed on the display screen so that a peripheral region adjoining the enlargement target region is displayed between these two regions.
摘要翻译：一种图像显示方法和装置，用于通过自动布置放大图像，在显示屏幕上同时显示整个原始图像及其放大图像的放大目标。该图像显示装置包括用于显示整个原始图像的整个原始图像的一部分的放大图像的显示器，包括叠加在整个原始图像上的关系中的字符，图案等，用于指定整个原始图像中的放大目标的输入装置，以及用于优先指定和计算放大对象区域的区域的值，放大图像显示区域的面积和放大率的自动布置装置，以使这些值中的一个最大化，并且基于计算结果。此外，为了使放大图像容易可见，放大对象区域和放大图像显示区域被布置并显示在显示屏幕上，使得在这两个区域之间显示与放大对象区域相邻的外围区域。

65. 发明授权

US06176986B1 Sputtering target of dielectrics having high strength and a method for manufacturing same 失效
标题翻译：具有高强度的电介质的溅射靶及其制造方法
公开(公告)号：US06176986B1
公开(公告)日：2001-01-23
申请号：US08863194
申请日：1997-05-27
申请人： Kazuo Watanabe , Akifumi Mishima
发明人： Kazuo Watanabe , Akifumi Mishima
IPC分类号： C23C1434
CPC分类号： C23C14/3414 , C04B35/465 , H01L21/31691
摘要： A dielectric sputtering target of high strength comprising a sintered barium, strontium titanate body, which is oxygen deficient, of the formula: Ba1-xSrxTiO3-y, wherein 0
摘要翻译：一种高强度的电介质溅射靶，其特征在于，其中0

66. 发明授权

US6137733A Boosting circuit using 2-step boosting operation 有权
标题翻译：升压电路采用两步升压操作
公开(公告)号：US6137733A
公开(公告)日：2000-10-24
申请号：US411365
申请日：1999-10-04
申请人： Kazuo Watanabe
发明人： Kazuo Watanabe
IPC分类号： G11C5/14 , G11C16/06 , G11C16/04
CPC分类号： G11C16/06 , G11C5/145
摘要： A semiconductor memory device with a boosting circuit includes a first power supply line, a second power supply line supplying a power supply potential, first and second boosting capacitors connected to the first power supply line, and a control circuit. The control circuit connects the second power supply line to the first power supply line for a first time interval such that the first power supply line and the first and second boosting capacitors, boosts the first power supply line and the second boosting capacitor by the first boosting capacitor for a second time interval after the first time interval, and boosts the first power supply line by the second boosting capacitor for a third time interval after the second time interval.
摘要翻译：具有升压电路的半导体存储器件包括第一电源线，提供电源电位的第二电源线，连接到第一电源线的第一和第二升压电容器以及控制电路。所述控制电路将所述第二电源线与所述第一电源线连接第一时间间隔，使得所述第一电源线和所述第一和第二升压电容器通过所述第一升压将所述第一电源线和所述第二升压电容器升压电容器，在第一时间间隔之后的第二时间间隔，并且在第二时间间隔之后，通过第二升压电容器将第一电源线升压第三时间间隔。

67. 发明授权

US5903730A Method of visualizing results of performance monitoring and analysis in a parallel computing system 失效
标题翻译：在并行计算系统中可视化性能监控和分析结果的方法
公开(公告)号：US5903730A
公开(公告)日：1999-05-11
申请号：US800381
申请日：1997-02-14
申请人： Noboru Asai , Tohru Matsumoto , Kazuo Watanabe
发明人： Noboru Asai , Tohru Matsumoto , Kazuo Watanabe
IPC分类号： G06F9/06 , G06F11/32 , G06F11/34 , G06F15/16 , G06F15/177 , G06F9/22
CPC分类号： G06F11/323 , G06F11/3404 , G06F11/3419
摘要： A method of visualizing the results of performance monitoring and analysis for a parallel computing system in which a plurality of processors execute a parallel processing program composed of a plurality of routines. First, information on the execution time of each routine is collected in a realtime manner while the program is concurrently executed by the plurality of processors. Second, a maximum, average, and minimum values of the execution time of each routine are calculated, based on the information collected for the plurality of processors. Third, the collected information is summarized as an execution profile and displayed in graphical form by using bar graphs, pie graphs, or radar charts. For each procedure or program loop, the present method clarifies the percentages of net user program execution, communication, synchronization, and other parallelization overheads, as well as indicating their deviations. This feature helps the user to understand the actual program behavior and to tune up the parallel processing program.
摘要翻译：一种可视化并行计算系统的性能监视和分析结果的方法，其中多个处理器执行由多个例程组成的并行处理程序。首先，在多个处理器同时执行程序的同时，以实时的方式收集关于每个程序的执行时间的信息。第二，基于为多个处理器收集的信息，计算每个例程的执行时间的最大值，平均值和最小值。第三，收集的信息被总结为执行简档，并通过使用条形图，饼图或雷达图表以图形形式显示。对于每个过程或程序循环，本方法阐明净用户程序执行，通信，同步和其他并行化开销的百分比，以及指示它们的偏差。此功能可帮助用户了解实际的程序行为并调整并行处理程序。

68. 发明授权

US5841711A Semiconductor memory device with redundancy switching method 失效
标题翻译：具有冗余切换方式的半导体存储器件
公开(公告)号：US5841711A
公开(公告)日：1998-11-24
申请号：US918668
申请日：1997-08-28
申请人： Kazuo Watanabe
发明人： Kazuo Watanabe
IPC分类号： G11C11/413 , G06F12/16 , G11C11/401 , G11C29/00 , G11C29/10 , G11C29/44 , G11C7/00
CPC分类号： G11C29/789 , G11C29/44 , G11C29/10
摘要： A semiconductor memory device with a redundancy switching system is operable in first and second modes. In the first mode, data read from a memory element is compared with external data, and if the compared data do not agree with each other, an external address is latched. In the second mode, the latched external address is written into a redundancy switching nonvolatile memory element. The first and second modes are selected with the same signal for each memory chip.
摘要翻译：具有冗余切换系统的半导体存储器件可在第一和第二模式中操作。在第一模式中，将从存储元件读取的数据与外部数据进行比较，如果所比较的数据彼此不一致，则锁存外部地址。在第二模式中，锁存的外部地址被写入冗余开关非易失性存储元件。对于每个存储器芯片，以相同的信号选择第一和第二模式。

69. 发明授权

US5776545A Nozzle coating method and equipment 失效
标题翻译：喷嘴涂布方法和设备
公开(公告)号：US5776545A
公开(公告)日：1998-07-07
申请号：US717348
申请日：1996-09-20
申请人： Hiroshi Yoshiba , Yoichiro Ohashi , Kazuo Watanabe , Kazuyuki Shiozaki
发明人： Hiroshi Yoshiba , Yoichiro Ohashi , Kazuo Watanabe , Kazuyuki Shiozaki
IPC分类号： B05D1/02 , B05D1/26 , C03C17/00 , C03C17/04 , H01J9/02 , B05D3/12
CPC分类号： B05D1/26 , C03C17/002 , C03C17/04
摘要： A method and an equipment in which a comparatively thick film such as the barrier rib of a plasma display panel is formed by one time of coating process. According to the nozzle coating equipment (10), a coating line (21A) is formed in such a way that, while a coating solution is being discharged from the tip of a nozzle (20) which is provided at the lower end of a liquid vessel (18) filled with the coating solution, the liquid vessel (18) carrying the nozzle (20) is driven in an X-direction relatively to a glass plate (16). Subsequently, the liquid vessel (18) is shifted in a Y-direction to the amount of a pitch P which is smaller than the width of each coating line, whereupon the next coating line (21B) is formed. Thus, a coated surface (22) is formed on the glass plate (16) in such a manner that the adjacent coating lines overlap each other in the widthwise direction thereof in succession.
摘要翻译：通过一次涂布工艺形成诸如等离子体显示面板的隔壁的比较厚的膜的方法和设备。根据喷嘴涂布设备（10），涂布线（21A）以这样一种方式形成，即当涂布液从设置在液体的下端的喷嘴（20）的末端排出时填充有涂布溶液的容器（18），携带喷嘴（20）的液体容器（18）相对于玻璃板（16）沿X方向驱动。随后，液体容器（18）沿Y方向移动到距每个涂布线的宽度小的间距P的量，从而形成下一个涂布线（21B）。因此，在玻璃板（16）上形成涂层表面（22），使得相邻的涂布线在宽度方向上相互重叠。

70. 发明授权

US5761128A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5761128A
公开(公告)日：1998-06-02
申请号：US827056
申请日：1997-03-26
申请人： Kazuo Watanabe
发明人： Kazuo Watanabe
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , G11C16/20 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/36 , G11C29/44 , G11C29/48 , G11C13/00
CPC分类号： G11C29/835 , G11C16/20 , G11C29/36 , G11C29/44 , G11C29/48
摘要： An EPROM has a main memory cell block, test memory cell block and a redundant memory cell block in a memory cell array. The test memory cell block stores a test pattern for a device test after fabrication and a signature code including a maker code and a device code. If some memory cell group in the main memory cell block are substituted for by memory cell group in the redundant memory cell block, the corresponding bit of the signature code is generated by a signature code generator in accordance with the data for the faulty group. The signature code generator selects data read from the redundant memory cell block or the generated bit of the signature code depending on the mode of the memory device.
摘要翻译： EPROM在存储单元阵列中具有主存储单元块，测试存储单元块和冗余存储单元块。测试存储单元块在制造之后存储用于器件测试的测试图案和包括制造商代码和器件代码的签名代码。如果主存储器单元块中的一些存储单元组被冗余存储单元块中的存储单元组代替，那么签名代码的相应位根据有故障组的数据由签名代码生成器生成。签名代码生成器根据存储器件的模式选择从冗余存储器单元块读取的数据或签名代码的生成位。

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