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61. 发明申请

US20080191320A1 TRENCH WIDENING WITHOUT MERGING 有权
标题翻译：没有合并的TRENCH扩大
公开(公告)号：US20080191320A1
公开(公告)日：2008-08-14
申请号：US12103000
申请日：2008-04-15
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L29/04
CPC分类号： H01L29/945 , H01L29/66181
摘要： A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
摘要翻译：半导体结构。半导体结构包括半导体衬底，半导体衬底中的沟槽。沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。该方法还包括以下步骤：除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围周围。

62. 发明授权

US07384829B2 Patterned strained semiconductor substrate and device 有权
标题翻译：图形应变半导体衬底和器件
公开(公告)号：US07384829B2
公开(公告)日：2008-06-10
申请号：US10710608
申请日：2004-07-23
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/823412 , H01L29/739 , H01L29/78687
摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.
摘要翻译：一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。该结构包括具有图案化的应变和非应变材料的多层基底。

63. 发明申请

US20080132029A1 TRENCH WIDENING WITHOUT MERGING 失效
标题翻译：没有合并的TRENCH扩大
公开(公告)号：US20080132029A1
公开(公告)日：2008-06-05
申请号：US11957615
申请日：2007-12-17
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L21/76
CPC分类号： H01L29/945 , H01L29/66181
摘要： A semiconductor fabrication method. First, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench includes a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. Next, portions of the blocking layer on the {110} side wall surfaces are removed without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
摘要翻译：半导体制造方法。首先，提供半导体结构。半导体结构包括半导体衬底，半导体衬底中的沟槽。沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。接下来，除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围环境。

64. 发明申请

US20070273000A1 TRENCH WIDENING WITHOUT MERGING 有权
标题翻译：没有合并的TRENCH扩大
公开(公告)号：US20070273000A1
公开(公告)日：2007-11-29
申请号：US11420527
申请日：2006-05-26
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L29/00
CPC分类号： H01L29/945 , H01L29/66181
摘要： A semiconductor fabrication method comprises steps of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.
摘要翻译：半导体制造方法包括提供半导体结构的步骤。半导体结构包括半导体衬底，半导体衬底中的沟槽。沟槽包括侧壁，其包括{100}侧壁表面和{110}侧壁表面。半导体结构还包括在{100}侧壁表面和{110}侧壁表面上的阻挡层。该方法还包括以下步骤：除去{110}侧壁表面上的阻挡层的部分，而不去除{100}侧壁表面上的阻挡层的部分，使得{110}侧壁表面暴露于周围周围。

65. 发明申请

US20070045698A1 Semiconductor structures with body contacts and fabrication methods thereof 审中-公开
标题翻译：具有身体接触的半导体结构及其制造方法
公开(公告)号：US20070045698A1
公开(公告)日：2007-03-01
申请号：US11216395
申请日：2005-08-31
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L27/0218 , H01L27/10841 , H01L27/10864 , H01L27/10891
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.
摘要翻译：一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括构建在绝缘体上半导体（SOI）晶片上的多个垂直存储器单元和电耦合SOI的半导体本体和半导体衬底的主体接触晶圆。半导体本体包括用于垂直存储单元之一的存取装置的通道区域。延伸穿过SOI晶片的掩埋介电层的主体接触件提供电流泄漏路径，其减少浮体对垂直存储单元的影响。可以通过蚀刻延伸穿过SOI晶片的半导体主体和埋入介质层的通孔来形成本体接触，并且延伸到衬底中并且用导电材料部分地填充通孔，所述导电材料使半导体本体与衬底电耦合。

66. 发明授权

US07129129B2 Vertical device with optimal trench shape 失效
标题翻译：具有最佳沟槽形状的垂直装置
公开(公告)号：US07129129B2
公开(公告)日：2006-10-31
申请号：US10708861
申请日：2004-03-29
申请人： Thomas N. Adam , David C. Ahlgren , Kangguo Cheng , Ramachandra Divakaruni
发明人： Thomas N. Adam , David C. Ahlgren , Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L21/00
CPC分类号： H01L27/10876 , H01L27/10841 , H01L29/945 , Y10S438/931
摘要： A method of forming a trench in a semiconductor substrate includes a step of converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the litho for the active area, in particular a DRAM cell with a vertical transistor.
摘要翻译：在半导体衬底中形成沟槽的方法包括将沟槽的上部的横截面从八边形转换为矩形的步骤，从而减小了沟槽光刻和有源区光刻之间对准误差的敏感性。应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻层之间的未对准变得不敏感的垂直晶体管。

67. 发明申请

US20060071274A1 Method and structure for bonded silicon-on-insulator wafer 有权
标题翻译：粘合硅绝缘体晶片的方法和结构
公开(公告)号：US20060071274A1
公开(公告)日：2006-04-06
申请号：US10951745
申请日：2004-09-28
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L27/12 , H01L21/46
CPC分类号： H01L29/66772 , H01L21/304 , H01L21/30625 , H01L21/3065 , H01L21/76254 , H01L21/76275 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： A bonded SOI wafer and a method for forming a bonded SOI wafer are provided. According to the disclosed method, a first semiconductor wafer is provided, having a first dielectric layer disposed at an outer surface of the first wafer and a plurality of dielectric filled trenches extending from the outer surface inwardly into the semiconductor. The outer surface of the first wafer is bonded to the outer surface of a second semiconductor wafer to form a bonded wafer having a bulk semiconductor region, a buried dielectric layer overlying the bulk semiconductor region, and a semiconductor-on-insulator layer overlying the buried dielectric layer, with the dielectric filled trenches extending upwardly from the buried dielectric layer into the semiconductor-on-insulator layer. The thickness of the semiconductor-on-insulator layer is then reduced until uppermost surfaces of at least some of the dielectric filled trenches are at least partially exposed.
摘要翻译：提供键合SOI晶片和形成键合SOI晶片的方法。根据所公开的方法，提供第一半导体晶片，其具有设置在第一晶片的外表面处的第一介电层和从外表面向内延伸到半导体中的多个电介质填充沟槽。第一晶片的外表面被接合到第二半导体晶片的外表面，以形成具有体半导体区域，覆盖体半导体区域的掩埋电介质层和覆盖在掩埋层上的绝缘体上半导体层的键合晶片电介质层，其中介电填充的沟槽从掩埋介电层向上延伸到绝缘体上半导体层中。然后减小绝缘体上半导体层的厚度，直到至少一些电介质填充沟槽的最上表面至少部分露出。

68. 发明申请

US20050285175A1 Vertical SOI Device 审中-公开
标题翻译：垂直SOI器件
公开(公告)号：US20050285175A1
公开(公告)日：2005-12-29
申请号：US10710166
申请日：2004-06-23
申请人： Kangguo Cheng , Ramachandra Divakaruni , Oleg Glushenkov
发明人： Kangguo Cheng , Ramachandra Divakaruni , Oleg Glushenkov
IPC分类号： H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/78
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10888 , H01L27/1203
摘要： The present invention provides a structure and method of forming vertical transistors. The structure of the present invention comprises: a substrate having an insulator layer formed thereon and a trench formed therein, the trench having an upper trench section extending through the insulator layer to an upper surface of the substrate and having a lower trench section extending from the upper substrate surface into the substrate; a semiconductor layer formed adjacent to the upper trench sidewalls; an upper terminal region and a lower terminal region formed in the semiconductor layer, where a channel region separates the upper terminal region from the lower terminal region; a gate insulator extending from the upper terminal region to the lower terminal region and in contact with the channel region; and a gate conductor formed on the gate insulator, the gate insulator isolating the gate conductor from the channel region.
摘要翻译：本发明提供一种形成垂直晶体管的结构和方法。本发明的结构包括：具有形成在其上的绝缘体层和形成在其中的沟槽的衬底，所述沟槽具有延伸穿过绝缘体层的上沟槽部分到衬底的上表面，并且具有从上基板表面进入基板; 与所述上沟槽侧壁相邻形成的半导体层; 形成在半导体层中的上端子区域和下端子区域，其中沟道区域将上端子区域与下端子区域分开; 栅极绝缘体，其从所述上端子区域延伸到所述下端子区域并与所述沟道区域接触; 以及形成在栅极绝缘体上的栅极导体，栅极绝缘体将栅极导体与沟道区隔离。

69. 发明授权

US06969648B2 Method for forming buried plate of trench capacitor 有权
标题翻译：形成沟槽电容器掩埋板的方法
公开(公告)号：US06969648B2
公开(公告)日：2005-11-29
申请号：US10604081
申请日：2003-06-25
申请人： Kangguo Cheng , Ramachandra Divakaruni
发明人： Kangguo Cheng , Ramachandra Divakaruni
IPC分类号： H01L27/108 , H01L21/02 , H01L21/3215 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/60 , H01L21/3215 , H01L27/1087
摘要： A method for forming a buried plate in a trench capacitor is disclosed. The trench is completely filled with a dopant source material such as ASG. The dopant source material is then recessed and the collar material is deposited to form the collar in the upper portion of the trench. After drive-in of the dopants to form the buried plate, the dopant source material is removed and the collar materials may be removed.
摘要翻译：公开了一种在沟槽电容器中形成掩埋板的方法。沟槽完全填充有诸如ASG的掺杂剂源材料。然后掺杂剂源材料被凹入，并且沉积套环材料以在沟槽的上部形成套环。在掺杂剂掺入以形成掩埋板之后，去除掺杂剂源材料并且可以去除套环材料。

70. 发明申请

US20050255386A1 METHODS AND STRUCTURES FOR PROTECTING ONE AREA WHILE PROCESSING ANOTHER AREA ON A CHIP 失效
标题翻译：在芯片上处理其他区域时保护一个区域的方法和结构
公开(公告)号：US20050255386A1
公开(公告)日：2005-11-17
申请号：US10709514
申请日：2004-05-11
申请人： Deok-kee Kim , Kenneth Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Dirk Pfeiffer , Timothy Dalton , Katherina Babich , Arpan Mahorowala , Harald Okorn-Schmidt
IPC分类号： G03C5/00 , G03F7/11 , G03F9/00 , H01L21/033 , H01L21/311 , H01L21/331
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

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