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61. 发明申请

US20120193710A1 DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE 有权
标题翻译：减少接头泄漏的装置和方法
公开(公告)号：US20120193710A1
公开(公告)日：2012-08-02
申请号：US13446602
申请日：2012-04-13
申请人： Kanggou Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kanggou Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/78
CPC分类号： H01L29/66628 , H01L21/26513 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834
摘要： A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.
摘要翻译：用于减少半导体结中的结漏电的器件和方法包括在器件的源极/漏极区域中形成刻面的凸起结构。掺杂剂从小面凸起结构扩散到小平面凸起结构下面的基底中以形成源极/漏极区域。在刻面凸起结构上施加喷洒注入，以在源/漏区的衬底中产生多深度掺杂物分布。

62. 发明授权

US08304301B2 Implant free extremely thin semiconductor devices 有权
标题翻译：植入物非常薄的半导体器件
公开(公告)号：US08304301B2
公开(公告)日：2012-11-06
申请号：US12621299
申请日：2009-11-18
申请人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer. Epitaxially growing the extremely thin semiconductor layer on the Ge layer ensures good thickness control across the wafer. This process could be used for SOI or bulk wafers.
摘要翻译：公开了半导体器件和制造半导体器件的方法。在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。以这种方式，半导体层成为非常薄的绝缘体上半导体层。在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。在Ge层上外延生长极薄的半导体层确保跨晶片的良好的厚度控制。该工艺可用于SOI或体晶片。

63. 发明授权

US08008138B2 Extremely thin semiconductor on insulator semiconductor device with suppressed dopant segregation 有权
标题翻译：极薄的半导体绝缘体半导体器件具有抑制的掺杂剂分离
公开(公告)号：US08008138B2
公开(公告)日：2011-08-30
申请号：US12627424
申请日：2009-11-30
申请人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/78648 , H01L21/76251 , H01L21/84 , H01L29/66742 , H01L29/78603 , H01L29/78687
摘要： A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin semiconductor-on-insulator (ETSOI) layer, i.e., a semiconductor layer having a thickness of less than 20 nm. In one embodiment, the method begins with forming a first semiconductor layer and epitaxially growing a second semiconductor layer on a handling substrate. A first gate structure is formed on a first surface of the second semiconductor layer and source regions and drain regions are formed adjacent to the gate structure. The handling substrate and the first semiconductor layer are removed to expose a second surface of the second semiconductor layer that is opposite the first surface of the semiconductor layer. A second gate structure or a dielectric region is formed in contact with the second surface of the second semiconductor layer.
摘要翻译：提供一种制造半导体器件的方法，其中器件的沟道存在于极薄的绝缘体上半导体（ETSOI）层，即厚度小于20nm的半导体层中。在一个实施例中，该方法开始于形成第一半导体层并且在处理衬底上外延生长第二半导体层。第一栅极结构形成在第二半导体层的第一表面上，并且源极区和漏极区被形成为与栅极结构相邻。去除处理基板和第一半导体层以露出与半导体层的第一表面相对的第二半导体层的第二表面。形成与第二半导体层的第二表面接触的第二栅极结构或电介质区域。

64. 发明申请

US20110037125A1 EXTREMELY THIN SILICON ON INSULATOR (ETSOI) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) WITH IN-SITU DOPED SOURCE AND DRAIN REGIONS FORMED BY A SINGLE MASK 有权
标题翻译：绝缘子（ETSOI）的绝缘薄硅氧化物半导体（CMOS），具有由单个掩模形成的现场掺杂源和漏极区域
公开(公告)号：US20110037125A1
公开(公告)日：2011-02-17
申请号：US12542179
申请日：2009-08-17
申请人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/22 , H01L21/86
CPC分类号： H01L21/84 , H01L21/823814 , H01L21/845 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.
摘要翻译：提供一种制造电子结构的方法，其包括在衬底的SOI半导体层上形成第一导电掺杂的第一半导体材料。 SOI半导体层的厚度小于10nm。第一导电性原位掺杂的第一半导体材料从SOI半导体层的第一部分去除，其中第一导电性原位掺杂的第一半导体材料的剩余部分存在于SOI半导体层的第二部分上。第二导电性原位掺杂的第二半导体材料形成在SOI半导体层的第一部分上，其中掩模禁止在SOI半导体层的第二部分上形成第二导电性原位掺杂半导体材料。来自第一和第二导电性原位掺杂半导体材料的掺杂剂扩散到第一半导体层中以形成掺杂区域。

65. 发明授权

US08138543B2 Hybrid FinFET/planar SOI FETs 有权
标题翻译：混合FinFET /平面SOI FET
公开(公告)号：US08138543B2
公开(公告)日：2012-03-20
申请号：US12621460
申请日：2009-11-18
申请人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L27/01
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823878 , H01L27/1211 , H01L29/785
摘要： A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.
摘要翻译：公开了一种电路结构，其包含绝缘体上硅层（SOI）中的三种不同类型的器件中的至少一种：平面NFET器件，平面PFET器件和FinFET器件。沟槽隔离围绕平面NFET器件，并且平面PFET器件穿透SOI并邻接绝缘体。三种不同类型的器件中的每一种都包含高k栅极电介质层和中间间隙栅极金属层，每个包含相同的高k材料和相同的中间间隙金属。三种不同类型的设备中的每一种具有单独优化的阈值。还公开了一种用于制造电路结构的方法，该方法包括为三种不同类型的器件分别定义SOI中的部分：对于平面NFET器件，用于平面PFET器件和FinFET器件。该方法还包括共同沉积高k栅极电介质层和中间间隙栅极金属层，并且使用功函数修改层来单独调节各种器件的阈值。

66. 发明授权

US08084309B2 Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask 有权
标题翻译：非常薄的绝缘体上硅（ETSOI）互补金属氧化物半导体（CMOS），其具有由单个掩模形成的原位掺杂源极和漏极区域
公开(公告)号：US08084309B2
公开(公告)日：2011-12-27
申请号：US12542179
申请日：2009-08-17
申请人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/84 , H01L21/823814 , H01L21/845 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.
摘要翻译：提供一种制造电子结构的方法，其包括在衬底的SOI半导体层上形成第一导电掺杂的第一半导体材料。 SOI半导体层的厚度小于10nm。第一导电性原位掺杂的第一半导体材料从SOI半导体层的第一部分去除，其中第一导电性原位掺杂的第一半导体材料的剩余部分存在于SOI半导体层的第二部分上。第二导电性原位掺杂的第二半导体材料形成在SOI半导体层的第一部分上，其中掩模禁止在SOI半导体层的第二部分上形成第二导电性原位掺杂半导体材料。来自第一和第二导电性原位掺杂半导体材料的掺杂剂扩散到第一半导体层中以形成掺杂区域。

67. 发明申请

US20110115023A1 HYBRID FinFET/PLANAR SOI FETs 有权
标题翻译：混合FinFET /平面SOI FET
公开(公告)号：US20110115023A1
公开(公告)日：2011-05-19
申请号：US12621460
申请日：2009-11-18
申请人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823878 , H01L27/1211 , H01L29/785
摘要： A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.
摘要翻译：公开了一种电路结构，其包含绝缘体上硅层（SOI）中的三种不同类型的器件中的至少一种：平面NFET器件，平面PFET器件和FinFET器件。沟槽隔离围绕平面NFET器件，并且平面PFET器件穿透SOI并邻接绝缘体。三种不同类型的器件中的每一种都包含高k栅极电介质层和中间间隙栅极金属层，每个包含相同的高k材料和相同的中间间隙金属。三种不同类型的设备中的每一种具有单独优化的阈值。还公开了一种用于制造电路结构的方法，该方法包括为三种不同类型的器件分别定义SOI中的部分：对于平面NFET器件，用于平面PFET器件和FinFET器件。该方法还包括共同沉积高k栅极电介质层和中间间隙栅极金属层，并且使用功函数修改层来单独调节各种器件的阈值。

68. 发明授权

US08710588B2 Implant free extremely thin semiconductor devices 有权
标题翻译：植入物非常薄的半导体器件
公开(公告)号：US08710588B2
公开(公告)日：2014-04-29
申请号：US13595025
申请日：2012-08-27
申请人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.
摘要翻译：公开了半导体器件和制造半导体器件的方法。在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。以这种方式，半导体层成为非常薄的绝缘体上半导体层。在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。

69. 发明申请

US20130056802A1 IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES 有权
标题翻译：嵌入式无限超薄半导体器件
公开(公告)号：US20130056802A1
公开(公告)日：2013-03-07
申请号：US13595025
申请日：2012-08-27
申请人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Dechao Guo , Pranita Kulkarni , Philip J. Oldiges , Ghavam G. Shahidi
IPC分类号： H01L29/78
CPC分类号： H01L29/66636 , H01L29/66772 , H01L29/78621 , H01L29/78654
摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.
摘要翻译：公开了半导体器件和制造半导体器件的方法。在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。以这种方式，半导体层成为非常薄的绝缘体上半导体层。在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。

70. 发明申请

US20110127608A1 EXTREMELY THIN SEMICONDUCTOR ON INSULATOR SEMICONDUCTOR DEVICE WITH SUPPRESSED DOPANT SEGREGATION 有权
标题翻译：绝缘子半导体器件的超薄型半导体与抑制多边形分离
公开(公告)号：US20110127608A1
公开(公告)日：2011-06-02
申请号：US12627424
申请日：2009-11-30
申请人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L29/78648 , H01L21/76251 , H01L21/84 , H01L29/66742 , H01L29/78603 , H01L29/78687
摘要： A method of fabricating a semiconductor device is provided in which the channel of the device is present in an extremely thin semiconductor-on-insulator (ETSOI) layer, i.e., a semiconductor layer having a thickness of less than 20 nm. In one embodiment, the method begins with forming a first semiconductor layer and epitaxially growing a second semiconductor layer on a handling substrate. A first gate structure is formed on a first surface of the second semiconductor layer and source regions and drain regions are formed adjacent to the gate structure. The handling substrate and the first semiconductor layer are removed to expose a second surface of the second semiconductor layer that is opposite the first surface of the semiconductor layer. A second gate structure or a dielectric region is formed in contact with the second surface of the second semiconductor layer.
摘要翻译：提供一种制造半导体器件的方法，其中器件的沟道存在于极薄的绝缘体上半导体（ETSOI）层，即厚度小于20nm的半导体层中。在一个实施例中，该方法开始于形成第一半导体层并且在处理衬底上外延生长第二半导体层。第一栅极结构形成在第二半导体层的第一表面上，并且源极区和漏极区被形成为邻近栅极结构。去除处理基板和第一半导体层以暴露与半导体层的第一表面相对的第二半导体层的第二表面。形成与第二半导体层的第二表面接触的第二栅极结构或电介质区域。

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