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61. 发明授权

US09092218B2 Methods and apparatus to improve turbo performance for events handling 有权
标题翻译：提高事件处理的涡轮性能的方法和装置
公开(公告)号：US09092218B2
公开(公告)日：2015-07-28
申请号：US13156268
申请日：2011-06-08
申请人： Ryan D. Wells , Ohad Falik , Mary Jean Allarey
发明人： Ryan D. Wells , Ohad Falik , Jose P. Allarey
IPC分类号： G06F1/32 , G06F9/50
CPC分类号： G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/3237 , G06F1/3243 , G06F1/3246 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F1/3296 , G06F9/5027 , G06F9/5094 , G06F2209/501 , Y02D10/126 , Y02D10/17 , Y02D10/171 , Y02D10/22 , Y02D10/26 , Y02D50/20
摘要： Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.
摘要翻译：介绍了一种改善事件处理性能的装置的实施例。在一个实施例中，该装置包括多个处理元件和任务布线逻辑。如果至少一个处理元件处于turbo模式，则任务路由逻辑至少基于性能损失的比较来选择用于执行任务的处理元件。

62. 发明申请

US20140068281A1 MECHANISM FOR FACILITATING EFFICENT OPERATIONS PATHS FOR STORAGE DEVICES IN COMPUTING SYSTEMS 有权
标题翻译：促进计算机系统存储设备功能运行的机制
公开(公告)号：US20140068281A1
公开(公告)日：2014-03-06
申请号：US13596880
申请日：2012-08-28
申请人： Nimrod Diamant , Ohad Falik , Itay Franko , Robert W. Strong
发明人： Nimrod Diamant , Ohad Falik , Itay Franko , Robert W. Strong
IPC分类号： G06F1/00
CPC分类号： G06F1/3268 , Y02D10/154
摘要： A mechanism is described for facilitating efficient operations paths for storage devices in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes identifying a request for power mode change at a storage device at a computing system. The request for power mode change indicates potential reduced power state of the storage device. The method may further include transferring context information at the storage device to a host memory at the computing system, in response to the first command, and saving the context information at the host memory, wherein the storage device is at reduced power state.
摘要翻译：描述了根据本发明的一个实施例的用于促进用于计算系统中的存储设备的有效操作路径的机制。本发明的实施例的方法包括在计算系统处识别在存储设备处的功率模式改变的请求。电源模式更改请求表示存储设备的潜在降低功耗状态。该方法可以进一步包括响应于第一命令在存储设备处将上下文信息传送到计算系统的主机存储器，并将上下文信息保存在主机存储器处，其中存储设备处于降低的功率状态。

63. 发明授权

US08200879B1 Memory interface including an efficient variable-width bus 有权
标题翻译：存储器接口包括有效的可变宽度总线
公开(公告)号：US08200879B1
公开(公告)日：2012-06-12
申请号：US10934111
申请日：2004-09-03
申请人： Ohad Falik , Leonid Azriel
发明人： Ohad Falik , Leonid Azriel
IPC分类号： G06F13/40
CPC分类号： G11C5/02 , H01L24/05 , H01L25/0657 , H01L2224/48145 , H01L2224/49171 , H01L2225/06562 , H01L2924/01087 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2924/00012
摘要： A semiconductor device includes an interface controller for communication with a memory device over a communication link. The link includes a plurality of data lines for transmitting data. A plurality of bus width values are defined, each being a selectable number of data lines over which data are to be transmitted. The number of data lines is in the range between one and the number of the plurality of data lines. The interface controller is dynamically configurable to any of the defined bus width values, which becomes the current bus width. The transmission over each data line may be selectably in either direction. The transmission over all data lines corresponding to the current bus width may collectively carry, in at least one direction, command codes, memory addresses, and data in an intermixed manner.
摘要翻译：半导体器件包括用于通过通信链路与存储器件通信的接口控制器。链路包括用于发送数据的多条数据线。定义了多个总线宽度值，每个总线宽度值是数据要发送的可选数量的数据线。数据线的数量在多个数据线的一个和数量之间的范围内。接口控制器可动态配置为任何定义的总线宽度值，这将成为当前的总线宽度。每条数据线上的传输可以任意方向选择。对应于当前总线宽度的所有数据线上的传输可以在至少一个方向上以混合方式共同携带命令代码，存储器地址和数据。

64. 发明授权

US07890726B1 Flash memory protection scheme for secured shared BIOS implementation in personal computers with an embedded controller 有权
标题翻译：用于具有嵌入式控制器的个人计算机中的安全共享BIOS实现的闪存保护方案
公开(公告)号：US07890726B1
公开(公告)日：2011-02-15
申请号：US11894977
申请日：2007-08-22
申请人： Ohad Falik , Michal Schramm
发明人： Ohad Falik , Michal Schramm
IPC分类号： G06F12/00
CPC分类号： G06F13/1605 , G06F8/654 , G06F12/1425
摘要： An apparatus and method are disclosed. The apparatus allows dynamic setting of access permissions to contents of a shared memory in a memory device controlled by an embedded controller and allows updating and recovery of the contents. A computerized system comprising at least one Host linked to the memory device provides access paths to the shared memory, to the Host, and to the embedded controller. The memory device is partitioned into separate blocks, each of which is used to store different types of data. A location is designated in the shared memory for storing protection information that includes data related to access operations allowed by at least one access path to a part of the shared memory. Access, via an arbitration device, to separate parts of the shared memory is permitted by using an access control unit that enables/disables access to predetermined portions of the shared memory.
摘要翻译：公开了一种装置和方法。该装置允许对由嵌入式控制器控制的存储器件中的共享存储器的内容的访问许可权的动态设置，并允许更新和恢复内容。包括至少一个与存储器件连接的主机的计算机化系统提供到共享存储器，主机和嵌入式控制器的访问路径。存储器件被分割成单独的块，每个块用于存储不同类型的数据。在共享存储器中指定一个位置，用于存储保护信息，该保护信息包括与由共享存储器的一部分的至少一个访问路径允许的访问操作有关的数据。通过使用访问控制单元允许/禁止访问共享存储器的预定部分，通过仲裁设备访问共享存储器的单独部分。

65. 发明申请

US20100115240A1 Optimizing performance of instructions based on sequence detection or information associated with the instructions 有权
标题翻译：基于序列检测或与指令相关的信息优化指令的性能
公开(公告)号：US20100115240A1
公开(公告)日：2010-05-06
申请号：US12290962
申请日：2008-11-05
申请人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
发明人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
IPC分类号： G06F9/30 , G06F12/06
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/325 , G06F9/3855 , G06F9/3857
摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一个指令解码器，其可以接收输入指令和路径选择信号，并且响应于路径选择信号将输入指令解码为第一指令代码或第二指令代码。代表相同输入指令的两个不同的指令代码可以被执行单元用于执行针对不同数据长度优化的操作。描述和要求保护其他实施例。

66. 发明授权

US07579683B1 Memory interface optimized for stacked configurations 有权
标题翻译：针对堆叠配置优化的内存接口
公开(公告)号：US07579683B1
公开(公告)日：2009-08-25
申请号：US10934113
申请日：2004-09-03
申请人： Ohad Falik , Aviv Melinovitch
发明人： Ohad Falik , Aviv Melinovitch
IPC分类号： H01L23/48
CPC分类号： G11C5/02 , H01L24/05 , H01L25/0657 , H01L2224/48145 , H01L2224/49171 , H01L2225/06562 , H01L2924/01087 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2924/00012
摘要： A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so that the circuit layout of the semiconductor die is invariable with respect to the size of the memory die within a given range of sizes.
摘要翻译：半导体管芯包括用于与存储管芯连接的多个互连焊盘。两个模具以堆叠的方式封装在一起。多个焊盘被布置成使得半导体管芯的电路布局相对于给定尺寸范围内的存储器管芯的尺寸是不变的。

67. 发明授权

US07318129B1 Flash memory protection scheme for secured shared BIOS implementation in personal computers with an embedded controller 有权
标题翻译：用于具有嵌入式控制器的个人计算机中的安全共享BIOS实现的闪存保护方案
公开(公告)号：US07318129B1
公开(公告)日：2008-01-08
申请号：US11301287
申请日：2005-12-12
申请人： Ohad Falik , Michal Schramm
发明人： Ohad Falik , Michal Schramm
IPC分类号： G06F12/14
CPC分类号： G06F13/1605 , G06F8/654 , G06F12/1425
摘要： An apparatus and method are disclosed for protecting the contents of a shared memory in a memory device controlled by an embedded controller. The apparatus allows dynamic setting of access permissions to said contents and allows updating and recovery of the contents. A computerized system comprising at least one Host linked to the memory device provides access paths to the shared memory, to the Host, and to the embedded controller. An arbitration device for allocating access paths to the memory device is also provided. The memory device is partitioned into separate blocks, each of which is used to store different types of data. A location is designated in the shared memory for storing protection information that includes data related to access operations allowed by at least one access path to a part of the shared memory. Access, via the arbitration device, to separate parts of the shared memory is permitted by using an access control unit that enables/disables access to predetermined portions of the hared memory by at least one of the access paths.
摘要翻译：公开了一种用于保护由嵌入式控制器控制的存储器件中的共享存储器的内容的装置和方法。该装置允许对所述内容的访问权限的动态设置，并且允许更新和恢复内容。包括至少一个与存储器件连接的主机的计算机化系统提供到共享存储器，主机和嵌入式控制器的访问路径。还提供了一种用于向存储设备分配访问路径的仲裁设备。存储器件被分割成单独的块，每个块用于存储不同类型的数据。在共享存储器中指定一个位置，用于存储保护信息，该保护信息包括与由共享存储器的一部分的至少一个访问路径允许的访问操作有关的数据。通过使用访问控制单元来允许通过仲裁设备访问共享存储器的单独部分，该访问控制单元能够通过至少一个访问路径来启用/禁用访问已存储的存储器的预定部分。

68. 发明授权

US07296124B1 Memory interface supporting multi-stream operation 有权
标题翻译：内存接口支持多流操作
公开(公告)号：US07296124B1
公开(公告)日：2007-11-13
申请号：US10933698
申请日：2004-09-03
申请人： Ohad Falik
发明人： Ohad Falik
IPC分类号： G06F9/26 , G06F9/34
CPC分类号： G06F13/1647
摘要： A memory device includes one or more memory arrays and an interface controller for exchanging memory contents data with a semiconductor device over a communication link. The exchanging of data occurs within sequential transactions. Each transaction is associated with a block of consecutive memory locations and with a starting address. The interface controller includes at least two address buffers, each for storing any of the starting addresses and any address obtained by incrementation thereof.
摘要翻译：存储器件包括一个或多个存储器阵列和用于通过通信链路与半导体器件交换存储器内容数据的接口控制器。数据交换发生在顺序交易中。每个事务与一个连续的存储单元块和起始地址相关联。接口控制器包括至少两个地址缓冲器，每个地址缓冲器用于存储任何起始地址和通过其增量获得的任何地址。

69. 发明申请

US20070157064A1 Systems and methods for error corrections 失效
标题翻译：纠错系统和方法
公开(公告)号：US20070157064A1
公开(公告)日：2007-07-05
申请号：US11325677
申请日：2006-01-05
申请人： Ohad Falik , Yuval Itkin
发明人： Ohad Falik , Yuval Itkin
IPC分类号： H03M13/00
CPC分类号： G06F11/1012 , H03M13/152 , H03M13/159 , H03M13/19 , H03M13/2906
摘要： Systems and methods for error correction of data. In one embodiment of the invention, a plurality of error correction schemes are applied when encoding data and depending on the circumstances, one or more of those schemes is selected to decode the data. In one of these embodiments, the applied error correction schemes include the BCH algorithm and the Hamming algorithm.
摘要翻译：用于数据纠错的系统和方法。在本发明的一个实施例中，在编码数据时应用多个纠错方案，并且根据情况，选择这些方案中的一个或多个来解码数据。在这些实施例中的一个中，应用的纠错方案包括BCH算法和汉明算法。

70. 发明授权

US07240222B1 Using ACPI power button signal for remotely controlling the power of a PC 有权
标题翻译：使用ACPI电源按钮信号远程控制PC的电源
公开(公告)号：US07240222B1
公开(公告)日：2007-07-03
申请号：US10375929
申请日：2003-02-27
申请人： Ohad Falik , Ilia Stolov
发明人： Ohad Falik , Ilia Stolov
IPC分类号： G06F1/00 , G06F11/30
CPC分类号： G06F1/3209
摘要： In a computer system that includes processing, memory and I/O modules and ACPI for outputting an ONCTL signal to a power supply unit. The power supply is configured to output a power off signal indicative of power off state and power on signal indicative of power on state. There is provided an embedded controller coupled to the ACPI and to the power supply unit. The embedded controller includes input for receiving a shut off event and in response to the shut off event, feeding to the ACPI a controller power off signal as long as the power supply is in power on state.
摘要翻译：在包括处理的计算机系统中，存储器和I / O模块以及用于将ONCTL信号输出到电源单元的ACPI。电源被配置为输出指示电源关闭状态的电源关闭信号和指示电源接通状态的上电信号。提供了耦合到ACPI和电源单元的嵌入式控制器。嵌入式控制器包括用于接收关闭事件的输入，并且响应于关断事件，只要电源处于通电状态，向ACPI馈送控制器断电信号。

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