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61. 发明申请

US20120169659A1 APPARATUS FOR CAPACITANCE SENSOR WITH INTERFERENCE REJECTION AND ASSOCIATED METHODS 审中-公开
标题翻译：具有干扰抑制和相关方法的电容传感器装置
公开(公告)号：US20120169659A1
公开(公告)日：2012-07-05
申请号：US13335407
申请日：2011-12-22
申请人： David R. Welland
发明人： David R. Welland
IPC分类号： G06F3/045
CPC分类号： G06F3/044 , G06F3/0416
摘要： A method for interfacing with a capacitive touch screen is disclosed. The method includes charging an internal capacitor in the touch screen, which internal capacitor is disposed proximate a fixed location on the touch screen and is capable of changing in response to a touch at that location on the touch screen. After charging, value of the charge on the internal capacitor is determined in a manner to reduce effects of interference.
摘要翻译：公开了一种用于与电容式触摸屏接口的方法。该方法包括对触摸屏中的内部电容器进行充电，该内部电容器设置在触摸屏上的固定位置附近，并且能够响应于触摸屏上该位置处的触摸而改变。充电后，以减少干扰影响的方式确定内部电容器的电荷值。

62. 发明授权

US08154336B2 Method and apparatus for reducing interference 有权
标题翻译：减少干扰的方法和装置
公开(公告)号：US08154336B2
公开(公告)日：2012-04-10
申请号：US11930596
申请日：2007-10-31
申请人： David R. Welland , Donald A. Kerth , Caiyi Wang
发明人： David R. Welland , Donald A. Kerth , Caiyi Wang
IPC分类号： H03K5/00
CPC分类号： H05K9/00 , H03L7/18 , H05K1/0216 , H05K3/10 , Y10T29/49124
摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.
摘要翻译：提供一种减少电路干扰的方法和装置。提供管理策略，以减少参考杂散和电路干扰。管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。这些技术可以单独使用，或者优选地彼此组合使用。

63. 发明申请

US20100102876A1 METHOD AND APPARATUS FOR REDUCING INTERFERENCE 审中-公开
公开(公告)号：US20100102876A1
公开(公告)日：2010-04-29
申请号：US12650545
申请日：2009-12-31
申请人： David R. Welland , Donald A. Kerth , Caiyi Wang
发明人： David R. Welland , Donald A. Kerth , Caiyi Wang
IPC分类号： H03B1/04
CPC分类号： H05K9/00 , H03L7/18 , H05K1/0216 , H05K3/10 , Y10T29/49124
摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

64. 发明授权

US07522193B2 Histogram-based automatic gain control method and system for video applications 有权
标题翻译：基于直方图的自动增益控制方法和视频应用系统
公开(公告)号：US07522193B2
公开(公告)日：2009-04-21
申请号：US10862488
申请日：2004-06-07
申请人： Nadi R. Itani , Caiyi Wang , David R. Welland
发明人： Nadi R. Itani , Caiyi Wang , David R. Welland
IPC分类号： H04N5/235 , H04N5/228 , H04N5/217
CPC分类号： H04N5/2352
摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括基于直方图的自动增益控制（AGC）电路，其首先通过调整所述CCD系统来控制增益，然后对于较高的增益电平进行增益，使所述 CDSVGA电路和数字增益电路，以产生组合的目标增益电平。一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC）耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

65. 发明授权

US07289145B2 Correlated double sampling variable gain amplifier circuit for use in a digital camera 有权
标题翻译：用于数码相机的相关双倍可变增益放大器电路
公开(公告)号：US07289145B2
公开(公告)日：2007-10-30
申请号：US11415000
申请日：2006-05-01
申请人： Sandra Marie Johnson , Shih-Chung Chao , Nadi Rafik Itani , Caiyi Wang , Brannon Craig Harris , Ash Prabala , Douglas R. Holberg , Alan Hansford , Syed Khalid Azim , David R. Welland
发明人： Sandra Marie Johnson , Shih-Chung Chao , Nadi Rafik Itani , Caiyi Wang , Brannon Craig Harris , Ash Prabala , Douglas R. Holberg , Alan Hansford , Syed Khalid Azim , David R. Welland
IPC分类号： H04N5/235
CPC分类号： H04N5/3575 , H04N5/335 , H04N5/361
摘要： An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.
摘要翻译：用于电荷耦合器件（CCD）或CMOS成像系统的图像处理器系统包括用于从CCD系统接收数据的相关双样本和可变增益（CDSVGA）电路以及首先通过调整来控制增益的自动增益控制（AGC）电路所述CCD系统然后为了更高的增益水平，使得所述CDSVGA电路和数字增益电路中的增益调整产生组合的目标增益电平。一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC）耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路。处理电路包括模拟前端和数字信号处理系统，用于捕获全运动视频并输出CCIR 601 4：2：2 YCrCb视频数据输出以便呈现在用户选择的显示器上。

66. 发明授权

US06903617B2 Method and apparatus for synthesizing high-frequency signals for wireless communications 有权
公开(公告)号：US06903617B2
公开(公告)日：2005-06-07
申请号：US10081730
申请日：2002-02-22
申请人： Lysander Lim , David R. Welland , John B. Pavelka , Edmund G. Healy
发明人： Lysander Lim , David R. Welland , John B. Pavelka , Edmund G. Healy
IPC分类号： H01L23/66 , H03B5/00 , H03L7/099 , H03L7/10 , H03L7/18 , H03L7/199 , H03K3/02
CPC分类号： H03L7/10 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/05554 , H01L2224/16 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H03L7/099 , H03L7/18 , H03L7/199 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/0401
摘要： A semiconductor package includes a package substrate and an integrated circuit. The package substrate has a first surface. The integrated circuit couples electrically to the first surface of the package substrate. The integrated circuit and the package substrate together form the semiconductor package. The semiconductor package also includes a first inductance circuit and a second inductance circuit, both formed within the semiconductor package. The first and second inductance circuits couple to each other in parallel. The first and second inductance circuits have substantially symmetrical geometric characteristics.

67. 发明授权

US06727754B2 RF power detector 有权
标题翻译：射频功率检测器
公开(公告)号：US06727754B2
公开(公告)日：2004-04-27
申请号：US09842456
申请日：2001-04-26
申请人： Timothy J. Dupuis , David R. Welland , Ali M. Niknejad , Susanne A. Paul
发明人： Timothy J. Dupuis , David R. Welland , Ali M. Niknejad , Susanne A. Paul
IPC分类号： H03F345
CPC分类号： H03F3/2176 , H01L23/645 , H01L23/66 , H01L2223/6644 , H01L2224/16 , H01L2224/16227 , H01L2224/16235 , H01L2924/00014 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H03F1/02 , H03F3/195 , H03F3/211 , H03F3/2171 , H03F3/2173 , H03F3/24 , H03F3/30 , H03F3/45179 , H03F3/72 , H03F2200/387 , H03F2200/391 , H03F2200/451 , H03K17/04163 , H03K17/6872 , Y10S257/904 , H01L2224/0401
摘要： A method and apparatus is provided for detecting the output power of an RF power amplifier for purposes of controlling the output power. A circuit for generating an output power control signal includes a power detector to detect the output power of an RF power amplifier. A variable gain amplifier is coupled to the power detector for amplifying the output of the power detector. The value of the generated control signal is a function of the gain of the variable gain amplifier.
摘要翻译：提供了一种用于检测RF功率放大器的输出功率以便控制输出功率的方法和装置。用于产生输出功率控制信号的电路包括检测RF功率放大器的输出功率的功率检测器。可变增益放大器耦合到功率检测器，用于放大功率检测器的输出。所生成的控制信号的值是可变增益放大器的增益的函数。

68. 发明授权

US06549765B2 Phase locked loop circuitry for synthesizing high-frequency signals and associated method 有权
标题翻译：用于合成高频信号和相关方法的锁相环电路
公开(公告)号：US06549765B2
公开(公告)日：2003-04-15
申请号：US09933530
申请日：2001-08-20
申请人： David R. Welland , Caiyi Wang
发明人： David R. Welland , Caiyi Wang
IPC分类号： H04B126
CPC分类号： H03L7/193 , H03J2200/10 , H03L7/099 , H03L7/10 , H03L7/18 , H03L7/199 , H03L7/23 , H03L2207/06
摘要： A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.
摘要翻译：用于合成诸如无线通信信号的高频信号的方法和装置包括具有可变电容电压控制振荡器（VCO）的锁相环（PLL）频率合成器，其具有连续变量的离散可变电容电容。离散可变电容可以提供可变电容的粗调谐调整，以补偿电容器和电感器公差，并将输出频率调整为接近期望的频率输出。连续可变电容可以提供可变电容的微调调整，以将输出频率聚焦以精确地匹配期望的频率输出。在微调调整期间，PLL可以由多个模拟控制信号控制。可以通过首先从VCO输出时钟的分割版本产生多个相移信号来导出模拟控制信号。第二，可以检测多个相移信号和参考时钟的分割版本之间的相位差，然后转换成模拟控制信号。

69. 发明授权

US06285536B1 High voltage input pad system 有权
标题翻译：高压输入板系统
公开(公告)号：US06285536B1
公开(公告)日：2001-09-04
申请号：US09433812
申请日：1999-11-03
申请人： Douglas R. Holberg , Nadi R. Itani , David R. Welland
发明人： Douglas R. Holberg , Nadi R. Itani , David R. Welland
IPC分类号： H02H900
CPC分类号： H01L27/0251 , H01L27/0248
摘要： A high voltage input pad and method for accepting electrostatic discharge (ESD) surges without damage to an input semiconductor amplifier. The protection system includes a metal gate, transistor, and n-well resistors which provide ESD protection. Protection is further provided against large voltages coupled to an amplifier by connecting an input bipolar junction transistor to the negative input connection of the amplifier. Negative surges are directed to ground with an anode grounded diode connected at its cathode to the negative input connection of the amplifier.
摘要翻译：高压输入焊盘和接受静电放电（ESD）浪涌而不损坏输入半导体放大器的方法。保护系统包括提供ESD保护的金属栅极，晶体管和n阱电阻。通过将输入双极结晶体管连接到放大器的负输入连接，进一步提供与放大器耦合的大电压的保护。负极电流被引导到地，其阳极接地二极管在其阴极处连接到放大器的负输入连接。

70. 发明授权

US06233441B1 Method and apparatus for generating a discretely variable capacitance for synthesizing high-frequency signals for wireless communications 失效
标题翻译：用于选择电容量以改变频率合成器的输出频率的方法和装置
公开(公告)号：US06233441B1
公开(公告)日：2001-05-15
申请号：US09086917
申请日：1998-05-29
申请人： David R. Welland
发明人： David R. Welland
IPC分类号： H04B106
CPC分类号： H03L7/091 , H03L7/07 , H03L7/0891 , H03L7/099 , H03L7/18
摘要： A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, a plurality of connected capacitor circuits for the discretely variable capacitance are disclosed each having a first switch that selectively couples a capacitor between two nodes. A multiple-bit digital control signal is also disclosed that couples to the control nodes of the plurality of switches to select an overall capacitance for the discretely variable capacitance circuit, with at least two of the capacitors have different capacitance values with respect to each other.
摘要翻译：公开了一种用于合成高频信号的方法和装置，其克服了与现有实施相关的集成问题，同时满足苛刻的相位噪声和其他杂质要求。在一个实施例中，公开了具有可变电容的压控振荡器（VCO）的锁相环（PLL）频率合成器，该可变电容包括连续可变电容的离散可变电容。离散可变电容可以提供可变电容的粗调谐调节，并且连续可变电容可以提供可变电容的精细调谐。更详细地，公开了用于离散可变电容的多个连接的电容器电路，每个具有选择性地在两个节点之间耦合电容器的第一开关。还公开了一种多位数字控制信号，其耦合到多个开关的控制节点以选择用于离散可变电容电路的总体电容，其中至少两个电容器具有彼此不同的电容值。

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