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61. 发明授权

US09203437B2 Circuitry and method for correcting 3-bit errors containing adjacent 2-bit error 有权
标题翻译：用于校正包含相邻2位错误的3位错误的电路和方法
公开(公告)号：US09203437B2
公开(公告)日：2015-12-01
申请号：US13720780
申请日：2012-12-19
申请人： Thomas Kern , Ulrich Backhausen , Thomas Rabenalt , Christian Badack , Michael Goessel
发明人： Thomas Kern , Ulrich Backhausen , Thomas Rabenalt , Christian Badack , Michael Goessel
IPC分类号： H03M13/15 , H03M13/00 , H03M13/53
CPC分类号： H03M13/152 , H03M13/1575 , H03M13/616
摘要： A circuitry is proposed for the correction of errors in a possibly erroneous binary word v′=v′1, . . . , v′n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n′ column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.
摘要翻译：提出了用于校正可能错误的二进制字v'= v'1中的错误的电路。。。，v'n相对于码字v = v1，。。。，vn，特别是包含相邻2位错误（突发错误）的3位错误。电路包括校正子发生器和解码器。使用修改的BCH，其中第一BCH码子矩阵的n个列向量作为列向量对配对，使得每个列向量对的两个列向量的分量XOR组合产生与所有列不同的相同列向量K 第一个BCH子矩阵的向量。第二BCH子矩阵包括根据第一BCH子矩阵中的列向量的伽罗瓦域算术的作为第三功率的相应的列向量。可以针对第一和第二子矩阵的列检查由发生器产生的综合征。

62. 发明授权

US08947784B2 Variable focus lens having two liquid chambers 有权
标题翻译：具有两个液体室的可变焦距透镜
公开(公告)号：US08947784B2
公开(公告)日：2015-02-03
申请号：US13823034
申请日：2010-10-26
申请人： Thomas Kern
发明人： Thomas Kern
IPC分类号： G02B3/14 , B29D11/00 , G02B26/00
CPC分类号： G02B3/14 , B29D11/00403 , G02B26/004
摘要： A variable focus lens has a housing (1) and an actuator (8) which are mutually displaceable along an optical axis (A) of the lens. A primary membrane (15) is arranged between a first chamber (24, 26) and a second chamber (30, 32), with the first and second chambers being filled with liquids of similar density but different indices of refraction. First and second auxiliary membranes (19, 17) are provided for volume compensation. The first auxiliary membrane (19) forms a wall section of the first chamber (24, 26), and the second auxiliary membrane (17) forms a wall section of the second chamber (30, 32), at least one or both of the auxiliary membranes facing environmental air at its outer side.
摘要翻译：可变焦距透镜具有可沿着透镜的光轴（A）相互移位的壳体（1）和致动器（8）。初级膜（15）布置在第一室（24,26）和第二室（30,32）之间，其中第一和第二室充满类似密度但不同折射率的液体。第一和第二辅助膜（19,17）用于体积补偿。第一辅助膜（19）形成第一腔室（24,26）的壁部分，第二辅助膜（17）形成第二腔室（30,32）的壁部分，至少一个或两个辅助膜在其外侧面向环境空气。

63. 发明授权

US08913435B2 Method and device for programming data into non-volatile memories 有权
标题翻译：用于将数据编程到非易失性存储器中的方法和装置
公开(公告)号：US08913435B2
公开(公告)日：2014-12-16
申请号：US13233292
申请日：2011-09-15
申请人： Ulrich Backhausen , Thomas Kern , Joerg Syassen
发明人： Ulrich Backhausen , Thomas Kern , Joerg Syassen
IPC分类号： G11C16/30 , G11C16/10
CPC分类号： G11C16/10
摘要： A device includes a non-volatile memory and a control unit, wherein the control unit is configured to change over programming of data of the non-volatile memory from a first programming mode to a second, different programming mode based on the occurrence of a control signal.
摘要翻译：一种设备包括非易失性存储器和控制单元，其中控制单元被配置为基于控制的发生将非易失性存储器的数据从第一编程模式切换到第二不同的编程模式信号。

64. 发明授权

US08898535B2 Apparatus and method for detecting an error within a coded binary word 有权
标题翻译：用于检测编码二进制字中的误差的装置和方法
公开(公告)号：US08898535B2
公开(公告)日：2014-11-25
申请号：US12959838
申请日：2010-12-03
申请人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
IPC分类号： H03M13/00 , H03M13/37 , H03M13/13 , H03M13/19
CPC分类号： H03M13/3776 , H03M13/13 , H03M13/19 , H03M13/3738
摘要： An apparatus for detecting an error within a coded binary word includes an error corrector and an error detector. The error corrector corrects a correctable bit error within a faulty subset of bits of a faulty coded binary word coded by an error correction code, so that the corrected subset of bits is equal to a corresponding subset of bits of a code word of the error correction code, if the error corrector works faultlessly. Further, the error detector determines an error detection bit sequence indicating whether or not an error detector input binary word is a code word of the error correction code. The error detector input binary word is based on a corrected coded binary word containing the corrected subset of bits and maximally a proper subset of bits of the faulty coded binary word.
摘要翻译：用于检测编码二进制字中的误差的装置包括误差校正器和误差检测器。误差校正器校正由错误校正码编码的故障编码二进制字的位的有故障子集内的可校正位错误，使得校正的位子集等于纠错码字的相应子集代码，如果错误校正器工作无效。此外，误差检测器确定指示误差检测器输入二进制字是否是纠错码的码字的错误检测比特序列。误差检测器输入二进制字基于包含校正的比特子集的校正的编码二进制字，并且最大限度地存在故障编码的二进制字的位的适当子集。

65. 发明授权

US08856629B2 Device and method for testing a circuit to be tested 有权
标题翻译：用于测试待测电路的装置和方法
公开(公告)号：US08856629B2
公开(公告)日：2014-10-07
申请号：US13606919
申请日：2012-09-07
申请人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
发明人： Thomas Kern , Ulrich Backhausen , Michael Goessel , Thomas Rabenalt
IPC分类号： H03M13/00 , G01R31/28 , G06F11/00
CPC分类号： G06F11/10 , G06F11/2215 , H03M13/09
摘要： A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v′)) based on a coded binary word (v′). The error syndrome bit sequence (s(v′)) indicates whether the coded binary word (v′) is a code word of an error correction code (C) used for coding the coded binary word (v′). The test sequence provider provides a test bit sequence (Ti) of the circuit that is different than the error syndrome bit sequence (s(v′)), if the error syndrome bit sequence (s(v′)) indicates that the coded binary word (v′) is a code word of the error correction code (C). The evaluation circuit detects an erroneous processing of the test bit sequence (Ti) by the circuit based on a test output signal (R(Ti)′)—caused by the test bit sequence (Ti)—of the circuit.
摘要翻译：用于测试电路的装置包括校正子确定器，测试序列提供器和评估电路。校正子确定器基于编码的二进制字（v'）来确定错误校正子位序列（s（v'））。误差校正位序列（s（v'））表示编码的二进制字（v'）是否是用于对编码的二进制字（v'）进行编码的纠错码（C）的码字。如果错误校正子序列（s（v'））指示编码的二进制码（s（v'）），则测试序列提供者提供与错误校正子比特序列（s（v'））不同的电路的测试比特序列（Ti）字（v'）是纠错码（C）的码字。评估电路基于由电路的测试比特序列（Ti）引起的测试输出信号（R（Ti）'）检测由该电路的测试比特序列（Ti）的错误处理。

66. 发明申请

US20140285911A1 Lens Assembly Apparatus And Method 审中-公开
标题翻译：镜头组装装置及方法
公开(公告)号：US20140285911A1
公开(公告)日：2014-09-25
申请号：US14212176
申请日：2014-03-14
申请人： Manuel Aschwanden , David Niederer , Thomas Schmidhausler , Christoph Romer , Thomas Kern , Shu-Heng Yang , Charles King , Dennis Ray Kirchhoefer , Daniel Warren
发明人： Manuel Aschwanden , David Niederer , Thomas Schmidhausler , Christoph Romer , Thomas Kern , Shu-Heng Yang , Charles King , Dennis Ray Kirchhoefer , Daniel Warren
IPC分类号： G02B7/10
CPC分类号： G02B7/10 , G02B3/14 , G02B7/04 , G02B7/182 , G02B26/0825 , H04N5/2254 , H04N5/2328
摘要： An optical apparatus includes a housing, a deformable lens, and a lens shaper. The lens shaper defines the shape of the deformable lens. A first mechanism is positioned within the housing to adjust an optical property of the deformable lens. A second mechanism is positioned within the housing to adjust an optical property of the deformable lens. The second mechanism is at least one of an electromechanical actuator or motor. The first mechanism and the second mechanism are different types of mechanisms.
摘要翻译：光学装置包括壳体，可变形透镜和透镜整形器。透镜整形器限定了可变形透镜的形状。第一机构定位在壳体内以调节可变形透镜的光学性质。第二机构定位在壳体内以调节可变形透镜的光学性质。第二机构是机电致动器或电动机中的至少一个。第一种机制和第二种机制是不同类型的机制。

67. 发明申请

US20140064011A1 System and Method for Providing Voltage Supply Protection in a Memory Device 有权
标题翻译：在存储器件中提供电压保护的系统和方法
公开(公告)号：US20140064011A1
公开(公告)日：2014-03-06
申请号：US13605129
申请日：2012-09-06
申请人： Jan Otterstedt , Wolf Allers , Mihail Jefremow , Edvin Paparisto , Leonardo Castro , Thomas Kern
发明人： Jan Otterstedt , Wolf Allers , Mihail Jefremow , Edvin Paparisto , Leonardo Castro , Thomas Kern
IPC分类号： G11C5/14
CPC分类号： G11C29/83 , G11C5/143 , G11C29/02 , G11C29/04 , G11C29/832
摘要： The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.
摘要翻译：本发明涉及一种电子存储器系统，更具体地说，涉及一种用于在存储器件中提供电压保护的系统，以及一种在存储器件中提供电压保护的方法。根据实施例，提供了一种用于在存储器件中提供电压保护的系统，该系统包括一个存储器阵列，该存储器阵列包括布置在多组存储器单元中的多个存储单元，以及多个限流元件，其中每组存储器单元与至少一个限流元件相关联。

68. 发明申请

US20140063923A1 Mismatch Error Reduction Method and System for STT MRAM 有权
标题翻译： STT MRAM的不匹配误差减少方法和系统
公开(公告)号：US20140063923A1
公开(公告)日：2014-03-06
申请号：US13605693
申请日：2012-09-06
申请人： Mihail Jefremow , Wolf Allers , Jan Otterstedt , Christian Peters , Thomas Kern
发明人： Mihail Jefremow , Wolf Allers , Jan Otterstedt , Christian Peters , Thomas Kern
IPC分类号： G11C7/06 , G11C11/16
CPC分类号： G11C11/1673
摘要： The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.
摘要翻译：本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。根据本发明的一个方面，一种用于读取存储单元的方法包括将来自存储单元的单元电流与来自参考源的参考电流组合以产生平均电流，使平均电流能够流过第一镜像晶体管在参考路径中的感测路径和第二镜像晶体管中，将电流失配存储在耦合到第一镜面晶体管和第二镜像晶体管的栅极的电容器上，将存储器单元与参考路径断开并将参考源与感测路径，使得电池电流仅能够流过感测路径，并且确定存储器单元的输出电平。

69. 发明申请

US20140056058A1 Differential Sensing Method and System for STT MRAM 有权
标题翻译： STT MRAM差分传感方法及系统
公开(公告)号：US20140056058A1
公开(公告)日：2014-02-27
申请号：US13592404
申请日：2012-08-23
申请人： Mihail Jefremow , Wolf Allers , Jan Otterstedt , Christian Peters , Thomas Kern
发明人： Mihail Jefremow , Wolf Allers , Jan Otterstedt , Christian Peters , Thomas Kern
IPC分类号： G11C7/12 , G11C11/16 , G11C7/00
CPC分类号： G11C29/028 , G11C11/16 , G11C11/1673 , G11C29/021 , G11C2029/5006
摘要： The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a system for reading a memory cell includes a read path and a precharge path. The reference current is provided through the read path and is sampled via a sampling element in the read path. Subsequently, a current from the memory cell is provided through the same sampling element and read path. The output level is then determined by the cell current working against the sampled reference current.
摘要翻译：本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。根据本发明的一个方面，用于读取存储单元的系统包括读取通道和预充电路径。参考电流通过读取路径提供，并通过读取路径中的采样元件进行采样。随后，通过相同的采样元件和读取路径提供来自存储单元的电流。然后，输出电平由针对采样参考电流工作的电池电流确定。

70. 发明授权

US08508287B2 Charge pumps with improved latchup characteristics 有权
标题翻译：具有改进闭锁特性的电荷泵
公开(公告)号：US08508287B2
公开(公告)日：2013-08-13
申请号：US12956225
申请日：2010-11-30
申请人： Thomas Kern , Ulrich Loibl
发明人： Thomas Kern , Ulrich Loibl
IPC分类号： G05F1/575 , G05F1/565 , H02M3/16
CPC分类号： H02M3/073 , H02M2003/071
摘要： Some embodiments of the present disclosure relate to regulators for charge pumps. Such regulators selectively activate a charge pump based not only on the voltage output of the charge pump, but also on an series of wake-up pulses that are delivered at predetermined time intervals and which are delivered independently of the voltage output of the charge pump. Hence, these wake-up pulses prevent extended periods of time in which the charge pump is inactive, thereby helping to prevent latch-up in some situations.
摘要翻译：本公开的一些实施例涉及电荷泵的调节器。这种调节器不仅基于电荷泵的电压输出而且基于以预定的时间间隔传送并且独立于电荷泵的电压输出传送的一系列唤醒脉冲来选择性地激活电荷泵。因此，这些唤醒脉冲防止电荷泵不活动的延长的时间段，从而有助于在某些情况下防止闩锁。

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