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61. 发明授权

US07084843B2 [Liquid crystal display panel's integrated driver device frame] 有权
标题翻译： [液晶显示面板的集成驱动装置框架]
公开(公告)号：US07084843B2
公开(公告)日：2006-08-01
申请号：US10604629
申请日：2003-08-06
申请人： Jian-Shen Yu , Wein-Town Sun
发明人： Jian-Shen Yu , Wein-Town Sun
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G2300/0408
摘要： An integrated driver device frame of a liquid crystal display panel is provided. The integrated driver device frame comprises a plurality of driver units, a plurality of driver lines and a plurality of output terminals. Each output terminal is coupled to a corresponding pixel element respectively. In the integrated driver device frame of the invention, the plurality of driver units is arranged with two staggered rows, in order that the driver unit width is larger than the interval of every neighboring two output terminals and is less than two times of the interval. Accordingly, the interval of two neighboring output terminals can be equal to the pixel pitch and the dot-per-inch resolution of the LCD panel can be enhanced.
摘要翻译：提供了一种液晶显示面板的集成驱动器装置框架。集成驱动器装置框架包括多个驱动器单元，多个驱动器线和多个输出端子。每个输出端分别耦合到相应的像素元件。在本发明的集成驱动器装置框架中，多个驱动器单元布置有两个交错列，以便驱动器单元宽度大于每个相邻两个输出端子的间隔，并且小于间隔的两倍。因此，两个相邻输出端子的间隔可以等于像素间距，并且可以提高LCD面板的每英寸点数分辨率。

62. 发明授权

US06924869B2 Display panel with the integrated driver circuit 有权
标题翻译：显示面板带有集成驱动电路
公开(公告)号：US06924869B2
公开(公告)日：2005-08-02
申请号：US10605162
申请日：2003-09-12
申请人： Jian-Shen Yu
发明人： Jian-Shen Yu
IPC分类号： G02F1/13 , G02F1/1339 , G02F1/1341 , G02F1/1345 , G02F1/1362
CPC分类号： G02F1/13454 , G02F1/1341
摘要： Display panel with the integrated driver circuit, the display panel comprises an isolating array substrate and further comprises a plurality of peripheral areas, a liquid crystal injection hole, display area, gate driver circuit and data driver circuit. This invention disposes the data driver circuit on the adjacent edge of the peripheral area, and disposes the liquid crystal injection hole on one peripheral area which is opposite to one of the adjacent edges. This invention makes it convenient to design the display panel.
摘要翻译：具有集成驱动电路的显示面板，显示面板包括隔离阵列基板，还包括多个外围区域，液晶注入孔，显示区域，栅极驱动电路和数据驱动电路。本发明将数据驱动电路配置在周边区域的相邻边缘，并将液晶注入孔配置在与相邻边缘之一相对的一个外围区域上。本发明使显示面板的设计变得方便。

63. 发明授权

US06680771B2 Thin film transistor liquid crystal display wherein the lower electrode includes a first electrode and a pixel electrode 有权
标题翻译：薄膜晶体管液晶显示器，其中下电极包括第一电极和像素电极
公开(公告)号：US06680771B2
公开(公告)日：2004-01-20
申请号：US10071062
申请日：2002-02-07
申请人： Jian-Shen Yu , Wei-Chih Chang
发明人： Jian-Shen Yu , Wei-Chih Chang
IPC分类号： G02F11343
CPC分类号： G02F1/133707 , G02F1/134336 , G02F1/1393 , G02F2001/134345
摘要： A thin film transistor liquid crystal display generates voltage difference between the lower electrodes, then the generating domains are controlled by the voltage difference. The lower electrode is divided into a narrow electrode and a pixel electrode. The pixel electrode is further divided into a plurality of pixel electrodes. The narrow electrode is coupled to a drain or a source of a thin film transistor, and a portion of the pixel electrode is overlapped on the drain/source of the thin film transistor but insulated to the drain/source of the thin film transistor to generate capacitive coupling and make the voltage level of the narrow electrode exceeds that of the pixel electrode. Thus, a horizontal electric fields is formed to generate multiple domains in a signal pixel.
摘要翻译：薄膜晶体管液晶显示器产生下电极之间的电压差，则产生区域受电压差的控制。下电极被分成窄电极和像素电极。像素电极被进一步分成多个像素电极。窄电极耦合到薄膜晶体管的漏极或源极，并且像素电极的一部分重叠在薄膜晶体管的漏极/源极上，但与薄膜晶体管的漏极/源极绝缘，以产生电容耦合，使得窄电极的电压电平超过像素电极的电压。因此，形成水平电场以在信号像素中产生多个畴。

64. 发明授权

US08614700B2 Voltage level shifter 有权
标题翻译：电压电平转换器
公开(公告)号：US08614700B2
公开(公告)日：2013-12-24
申请号：US13099462
申请日：2011-05-03
申请人： Jian-Shen Yu
发明人： Jian-Shen Yu
IPC分类号： G09G5/00
CPC分类号： G09G3/3685 , G09G2310/0289
摘要： A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.
摘要翻译：由单型晶体管形成的电压电平移位器包括两个输入端子，两个电源端子，多个薄膜晶体管和输出端子。由单一型晶体管形成的另一个电压电平移位器包括两个输入端子，一个输出端子，两个电源端子，两个输入单元，第一薄膜晶体管，禁用单元，反馈单元和第二薄膜晶体管。电压电平移位器由单型TFT形成。当将电压电平移位器集成到TFT显示器的基板中时，简化了制造工艺。此外，节电。

65. 发明授权

US08288774B2 Dual gate layout for thin film transistor 有权
标题翻译：薄膜晶体管的双栅极布局
公开(公告)号：US08288774B2
公开(公告)日：2012-10-16
申请号：US13348715
申请日：2012-01-12
申请人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
发明人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
IPC分类号： H01L29/10 , H01L29/76 , H01L31/036 , H01L31/112 , H01L29/04 , H01L31/0376 , H01L31/20 , H01L29/15 , H01L29/47 , H01L29/812 , H01L31/07 , H01L31/108
CPC分类号： H01L29/78645 , H01L27/12 , H01L29/42384 , H01L29/78621
摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout includes (1) a polysilicon on a substrate having a shaped of L- or of snake from top-view, having a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the poly-Si layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the poly-Si layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line through a source contact.
摘要翻译：公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。该布局包括（1）在基底上的多晶硅，其具有顶部具有L-或蛇形的形状，具有重掺杂的源极区，第一轻掺杂区，第一栅极通道，第二轻掺杂区，第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在具有扫描线的栅极氧化物层上形成栅极金属层，并且具有L形或I形的延伸部分。栅极金属与多晶硅层相交，限定了前述栅极沟道。在栅极通道中，至少有一个沿着信号线通过源极接触。

66. 发明授权

US07696972B2 Single clock driven shift register and driving method for same 有权
标题翻译：单时钟驱动移位寄存器和驱动方法相同
公开(公告)号：US07696972B2
公开(公告)日：2010-04-13
申请号：US11144939
申请日：2005-06-06
申请人： Jung-Chun Tseng , Sheng-Chao Liu , Jian-Shen Yu
发明人： Jung-Chun Tseng , Sheng-Chao Liu , Jian-Shen Yu
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/3674 , G09G3/3685 , G11C19/28
摘要： A single clock driven shift register comprising multiple stages is provided. The (M)th stage comprises a latch unit, a logic unit, and a non-overlap buffer. The latch unit latches an input signal from the (M−1)th stage according to a clock signal. The logic unit connecting to an output terminal of the latch unit deals with an output signal of the latch unit and the clock signal with an NAND logic calculation. The non-overlap buffer connecting to the output terminal of the logic unit comprises at least three inverters connected in a serial, and an output signal of the first inverter coupled to the output terminal of the logic unit is input to an latch unit of the (M+1)th stage. Meanwhile, an output signal of the non-overlap buffer of the (M−1)th stage is input to the non-overlap buffer or the logic unit to delay the output signal of the non-overlap buffer.
摘要翻译：提供包括多级的单个时钟驱动移位寄存器。第（M）级包括锁存单元，逻辑单元和非重叠缓冲器。锁存单元根据时钟信号锁存来自第（M-1）级的输入信号。连接到锁存单元的输出端的逻辑单元用NAND逻辑计算处理锁存单元的输出信号和时钟信号。连接到逻辑单元的输出端子的非重叠缓冲器包括串联连接的至少三个反相器，并且耦合到逻辑单元的输出端的第一反相器的输出信号被输入到 M + 1）级。同时，将第（M-1）级的非重叠缓冲器的输出信号输入到非重叠缓冲器或逻辑单元，以延迟非重叠缓冲器的输出信号。

67. 发明申请

US20090230403A1 Dual Gate Layout for Thin Film Transistor 有权
公开(公告)号：US20090230403A1
公开(公告)日：2009-09-17
申请号：US12469298
申请日：2009-05-20
申请人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
发明人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
IPC分类号： H01L29/786 , H01L33/00
CPC分类号： H01L29/78645 , H01L27/12 , H01L29/42384 , H01L29/78621
摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.

68. 发明授权

US07406146B2 Shift register circuit 有权
标题翻译：移位寄存器电路
公开(公告)号：US07406146B2
公开(公告)日：2008-07-29
申请号：US11550019
申请日：2006-10-17
申请人： Jian-Shen Yu
发明人： Jian-Shen Yu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register circuit includes a shift register unit and a buffer. The buffer is coupled to the output terminal of the shift register unit to delay the output signal from the shift register unit. The overlapped voltage of two output signals from two adjacent shift register units can be reduced.
摘要翻译：移位寄存器电路包括移位寄存器单元和缓冲器。缓冲器耦合到移位寄存器单元的输出端以延迟来自移位寄存器单元的输出信号。可以减少来自两个相邻移位寄存器单元的两个输出信号的重叠电压。

69. 发明申请

US20070177712A1 Dynamic Shift Register Circuit 有权
标题翻译：动态移位寄存器电路
公开(公告)号：US20070177712A1
公开(公告)日：2007-08-02
申请号：US11425022
申请日：2006-06-19
申请人： Jian-Shen Yu
发明人： Jian-Shen Yu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： An improved dynamic shift register circuit is disclosed. A circuit design is provided to minimize overlapping between two adjacent output pulses in the dynamic shift register circuit. In an application of analog sample-and-hold circuit, the circuit design effectively improves a distortion of sampled data caused by significant overlapping of two adjacent output pulses as control signals.
摘要翻译：公开了一种改进的动态移位寄存器电路。提供电路设计以最小化动态移位寄存器电路中的两个相邻输出脉冲之间的重叠。在模拟采样和保持电路的应用中，电路设计有效地改善了由两个相邻输出脉冲作为控制信号的重大重叠引起的采样数据失真。

70. 发明申请

US20050280030A1 Dual gate layout for thin film transistor 有权
标题翻译：薄膜晶体管的双栅极布局
公开(公告)号：US20050280030A1
公开(公告)日：2005-12-22
申请号：US11211606
申请日：2005-08-26
申请人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
发明人： Wein-Town Sun , Chun-Sheng Li , Jian-Shen Yu
IPC分类号： H01L27/12 , H01L29/423 , H01L29/786 , H01L29/739
CPC分类号： H01L29/78645 , H01L27/12 , H01L29/42384 , H01L29/78621
摘要： A dual gate layout of a thin film transistor of liquid crystal display to alleviate dark current leakage is disclosed. The layout comprises (1) a polysilicon on a substrate having a L-shaped or a snake shaped from top-view, which has a heavily doped source region, a first lightly doped region, a first gate channel, a second lightly doped region, a second gate channel, a third lightly doped region and a heavily doped drain region formed in order therein; (2) a gate oxide layer formed on the polysilicon layer and the substrate, (3) a gate metal layer then formed on the gate oxide layer having a scanning line and an extension portion with a L-shaped or an I-shaped. The gate metal intersects with the polysilicon layer thereto define the forgoing gate channels. Among of gate channels, at least one is along the signal line, which is connected to the source region through a source contact.
摘要翻译：公开了液晶显示器的薄膜晶体管的双栅极布局，以减轻暗电流泄漏。布局包括（1）在基板上具有从顶视图形成的L形或蛇形的多晶硅，其具有重掺杂的源极区，第一轻掺杂区，第一栅极沟道，第二轻掺杂区，第二栅极沟道，第三轻掺杂区和重掺杂漏极区; （2）形成在多晶硅层和基板上的栅极氧化层，（3）然后在栅极氧化物层上形成栅极金属层，栅极氧化物层具有扫描线和具有L形或I形的延伸部分。栅极金属与多晶硅层相交，限定了前述栅极沟道。在栅极通道中，沿着信号线至少有一个通过源极接触连接到源极区域。

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