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61. 发明授权

US09607877B2 Substrate structure, semiconductor device, and method for manufacturing the same 有权
公开(公告)号：US09607877B2
公开(公告)日：2017-03-28
申请号：US13376731
申请日：2011-03-04
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L23/34 , H01L27/12 , H05K7/20 , H01L21/762 , H01L27/06 , H01L27/088
CPC分类号： H01L21/76224 , H01L21/76283 , H01L27/0694 , H01L27/088
摘要： The present invention provides a substrate structure, a semiconductor device, and a manufacturing method thereof. The substrate structure comprises: a semiconductor substrate; and a first isolation region, wherein the first isolation region comprises: a first trench extending through the semiconductor substrate; and a first dielectric layer filling the first trench. Due to the isolation region extending through the substrate, it is possible to make device structures on both surfaces of the substrate, so as to increase the utilization of the substrate and the integration degree of the devices.

62. 发明授权

US09048286B2 Substrate for integrated circuit and method for forming the same 有权
标题翻译：集成电路基板及其形成方法
公开(公告)号：US09048286B2
公开(公告)日：2015-06-02
申请号：US13159351
申请日：2011-06-13
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , H01L21/7624 , H01L21/76283
摘要： The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.
摘要翻译：本发明涉及IC的基板及其制造方法。该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

63. 发明授权

US08987136B2 Semiconductor device and method for manufacturing local interconnect structure thereof 有权
标题翻译：半导体装置及其局部互连结构的制造方法
公开(公告)号：US08987136B2
公开(公告)日：2015-03-24
申请号：US13380061
申请日：2011-02-27
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/44 , H01L21/336 , H01L21/8234 , H01L29/78 , H01L21/768
CPC分类号： H01L29/78 , H01L21/76895 , H01L21/76897
摘要： A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.
摘要翻译：提供半导体器件和用于制造半导体器件的局部互连结构的方法。该方法包括在半导体衬底上的栅极的两侧上的侧壁间隔件和外侧壁间隔件之间形成可移除的牺牲侧壁间隔件，以及在侧壁间隔件和外侧壁之间的局部互连结构中的源极/漏极区域处形成接触通孔在去除牺牲侧壁间隔物之后立即在栅极的同一侧上间隔开。一旦源极/漏极通孔填充有导电材料以形成接触孔，接触孔的高度应与栅极的高度相同。在本地互连结构中，建立后续的第一金属布线层和源极/漏极区域或较低电平的栅极区域之间的电连接的接触通孔应制成相同的深度。

64. 发明授权

US08975700B2 Semiconductor device having a trench isolation structure 有权
标题翻译：具有沟槽隔离结构的半导体器件
公开(公告)号：US08975700B2
公开(公告)日：2015-03-10
申请号：US13380806
申请日：2011-08-09
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L27/12 , H01L29/78 , H01L21/84 , H01L21/8238
CPC分类号： H01L29/7849 , H01L21/823807 , H01L21/84 , H01L27/1203
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明实施例的半导体器件包括：基底，其包括基底层，基底层上的绝缘层和绝缘层上的半导体层; 以及形成在所述衬底上的第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管通过形成在所述衬底中的沟槽隔离结构彼此隔离。其中在第一和第二晶体管中的至少一个晶体管下方的基底层的至少一部分被应变，并且基底层的应变部分与绝缘层相邻。根据本发明的半导体器件增加了器件的速度，从而提高了器件的性能。

65. 发明授权

US08933504B2 Semiconductor structure and method for forming the semiconductor structure 有权
标题翻译：用于形成半导体结构的半导体结构和方法
公开(公告)号：US08933504B2
公开(公告)日：2015-01-13
申请号：US13807010
申请日：2011-11-30
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/265 , H01L29/66 , H01L29/45 , H01L29/49 , H01L29/786 , H01L21/822 , H01L21/84 , H01L27/06 , H01L27/12 , H01L27/115 , H01L21/28
CPC分类号： H01L29/7827 , H01L21/28008 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11556 , H01L27/1203 , H01L29/458 , H01L29/4908 , H01L29/66666 , H01L29/78642
摘要： The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.
摘要翻译：本发明公开了一种半导体结构，包括：衬底，导体层和围绕衬底上的导体层的电介质层; 覆盖所述导体层和所述电介质层的第一绝缘层; 形成在第一绝缘层上的栅极导体层和围绕栅极导体层的电介质层; 以及覆盖所述栅极导体层和围绕所述栅极导体层的所述电介质层的第二绝缘层; 其中填充有半导体材料的通孔垂直地穿过栅极导体层，通孔的底部停在导体层上，并且用作漏极/源极的第一导体插塞设置在通孔的顶部 ; 和用作源/漏电极的第二导体插头与导体层电接触，并且用作栅电极的第三导体插头电接触栅极导体层。

66. 发明授权

US08759923B2 Semiconductor device structure and method for manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US08759923B2
公开(公告)日：2014-06-24
申请号：US13131745
申请日：2011-02-25
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L27/088
CPC分类号： H01L29/78 , H01L21/76229 , H01L29/66477 , H01L29/665 , H01L29/66651 , H01L29/7831
摘要： The present invention provides a semiconductor device structure and a method for manufacturing the same. The method comprises: providing a semiconductor substrate, forming a first insulating layer on the surface of the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a stripe-type trench embedded in the first insulating layer and the semiconductor substrate; forming a channel region in the trench; forming a gate stack line on the channel region and source/drain regions on opposite sides of the channel region. Embodiments of the present invention are applicable to manufacture of semiconductor devices.
摘要翻译：本发明提供一种半导体器件结构及其制造方法。该方法包括：提供半导体衬底，在半导体衬底的表面上形成第一绝缘层; 形成嵌入在所述第一绝缘层和所述半导体衬底中的浅沟槽隔离体; 形成嵌入在所述第一绝缘层和所述半导体衬底中的条状沟槽; 在沟槽中形成沟道区; 在通道区域的相对侧上的沟道区域和源极/漏极区域上形成栅极堆叠线。本发明的实施例可应用于半导体器件的制造。

67. 发明申请

US20140110756A1 SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140110756A1
公开(公告)日：2014-04-24
申请号：US13981808
申请日：2012-07-24
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong , Hao Wu
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong , Hao Wu
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66477 , H01L21/2815 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78639 , H01L29/78654
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，该方法包括：在衬底上顺序形成牺牲层和半导体层; 在所述半导体层上形成第一覆盖层; 形成以第一覆盖层为掩模延伸到基板的开口; 通过所述开口选择性地去除所述牺牲层的至少一部分，并且由于去除所述牺牲层而在绝缘材料中填充绝缘材料; 在开口中形成源极和漏极区域之一; 在所述基板上形成第二覆盖层; 以第二覆盖层为掩模形成源区和漏区中的另一个; 去除所述第二覆盖层的一部分; 以及形成栅极电介质层，并且在所述第二覆盖层的剩余部分的侧壁上形成隔板形式的栅极导体。

68. 发明授权

US08703558B2 Graphene device and method for manufacturing the same 有权
标题翻译：石墨烯装置及其制造方法
公开(公告)号：US08703558B2
公开(公告)日：2014-04-22
申请号：US13140141
申请日：2011-02-24
申请人： Qingqing Liang , Zhi Jin , Wenwu Wang , Huicai Zhong , Xinyu Liu , Huilong Zhu
发明人： Qingqing Liang , Zhi Jin , Wenwu Wang , Huicai Zhong , Xinyu Liu , Huilong Zhu
IPC分类号： H01L21/00
CPC分类号： H01L29/778 , H01L29/1606 , H01L29/78603 , H01L29/78618 , H01L29/78684
摘要： The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.
摘要翻译：本发明提供了一种石墨烯器件结构及其制造方法，该器件结构包括石墨烯层; 与石墨烯层接触的栅极区域; 半导体掺杂区域形成在栅极区域的两个相对侧并与石墨烯层接触，其中半导体掺杂区域与栅极区域隔离; 在栅极区域上形成的触点和形成在半导体掺杂区域上的触点。通过半导体掺杂区域增加石墨烯器件的开关比，而不增加石墨烯材料的带隙，即不影响材料的迁移率或器件的速度，从而增加石墨烯材料的适用性在CMOS设备中。

69. 发明授权

US08691641B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08691641B2
公开(公告)日：2014-04-08
申请号：US13888930
申请日：2013-05-07
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/3086 , H01L21/76897 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7843 , H01L29/7848
摘要： A method of manufacturing a semiconductor device is provided, in which after forming a gate stack and a first spacer thereof, a second spacer and a third spacer are formed; and then an opening is formed between the first spacer and the third spacer by removing the second spacer. The range of the formation for the raised active area 220 is limited by forming an opening 214 between the first spacer 208 and the third spacer 212. The raised active area 220 is formed in the opening 214 in a self-aligned manner, so that a better profile of the raised active area 220 may be achieved and the possible shorts between adjacent devices caused by an unlimited manner may be avoided. Moreover, based on such a manufacturing method, it is easy to make the gate electrode 204 to be flushed with the raised active area 220, and is also easy to implement the dual stress nitride process so as to increase the mobility of the device.
摘要翻译：提供一种制造半导体器件的方法，其中在形成栅极堆叠及其第一间隔物之后，形成第二间隔物和第三间隔物; 然后通过移除第二间隔件在第一间隔件和第三间隔件之间形成开口。通过在第一间隔件208和第三间隔件212之间形成开口214来限制凸起的有效区域220的形成范围。凸起的有源区域220以自对准的方式形成在开口214中，使得可以实现凸起的有效区域220的更好的轮廓，并且可以避免由无限制的方式引起的相邻设备之间的可能的短路。此外，基于这样的制造方法，可以容易地利用凸起的有源区域220冲洗栅电极204，并且也容易实施双应力氮化物工艺，以增加器件的移动性。

70. 发明授权

US08525188B2 Shallow trench isolation structure and method for forming the same 有权
标题翻译：浅沟隔离结构及其形成方法
公开(公告)号：US08525188B2
公开(公告)日：2013-09-03
申请号：US13132068
申请日：2011-01-27
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L31/0312 , H01L29/00 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/76232
摘要： The invention provides a STI structure and method for forming the same. The STI structure includes a semiconductor substrate; a first trench embedded in the semiconductor substrate and filled up with a first dielectric layer; and a second trench formed on a top surface of the semiconductor substrate and interconnected with the first trench, wherein the second trench is filled up with a second dielectric layer, a top surface of the second dielectric layer is flushed with that of the semiconductor substrate, and the second trench has a width smaller than that of the first trench. The invention reduces dimension of divots and improves performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其形成方法。 STI结构包括半导体衬底; 第一沟槽，其嵌入在所述半导体衬底中并填充有第一介电层; 以及形成在所述半导体衬底的顶表面上并与所述第一沟槽互连的第二沟槽，其中所述第二沟槽填充有第二介电层，所述第二介电层的顶表面与所述半导体衬底的顶表面冲洗，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减小了图形的尺寸并提高了半导体器件的性能。

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