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    • 64. 发明授权
    • Switch for self-healing ring
    • 切换自愈环
    • US5475676A
    • 1995-12-12
    • US89948
    • 1993-07-12
    • Masahiro TakatoriYukio NakanoYoshihiro AshiHiroyuki Fujita
    • Masahiro TakatoriYukio NakanoYoshihiro AshiHiroyuki Fujita
    • H04J3/08H04Q11/04
    • H04J3/085
    • First stage and third stage four-input four-output space division switches are arranged before and after a second stage time division switch, and two outputs of the first stage space division switch and two inputs of the third stage space division switch are connected by bypassing the time division switch. The time division switch has n control memories. A first control memory stores connection information in a normal state of each path set in the transmission line, a second control memory stores connection information of a first alternative path when failures occur in a path, and an n-th control memory (n is any integer equal or greater than 3) stores connection information of an (n-1)th alternative path, and a control memory corresponding the a failure pattern is selected from the n control memories for each path.
    • 第一级和第三级四输入四输出空分开关布置在第二级分时开关之前和之后,第一级空分开关的两个输出和第三级空分开关的两个输入通过旁路连接 时分开关。 时分开关具有n个控制存储器。 第一控制存储器存储在传输线路中设置的每个路径的正常状态的连接信息,当路径中出现故障时,第二控制存储器存储第一替代路径的连接信息,并且第n控制存储器 整数等于或大于3)存储第(n-1)个替代路径的连接信息,并且从每个路径的n个控制存储器中选择与故障模式相对应的控制存储器。
    • 65. 发明授权
    • Routing method and apparatus for switching between routing and
conversion tables based on selection information included in cells to
be routed
    • 基于包括在要路由的单元中的选择信息,在路由和转换表之间切换的路由方法和装置
    • US5473598A
    • 1995-12-05
    • US744513
    • 1991-08-13
    • Masahiro TakatoriYukio NakanoYoshihiro AshiTadayuki Kanno
    • Masahiro TakatoriYukio NakanoYoshihiro AshiTadayuki Kanno
    • H04L12/70H04L12/931H04L12/947H04J3/26
    • H04L49/254H04L49/256H04L49/3009H04L49/3081H04L49/309H04L49/552H04L2012/5627
    • A cell routing method and apparatus in an ATM processing apparatus. The ATM processing apparatus has two or more routing tables associated with address filters of an ATM switch to store routing information for indicating the destination of cell output, and two or more conversion tables associated with VPI conversion circuits for replacing VPI (Virtual Path Identifier) or VCI conversion circuits for replacing VCI (Virtual Channel Identifier) to store information for indicating the VPI or VCI obtained after conversion. In an input interface circuit, selection information indicating which routing table and conversion table out of the above described two or more routing tables and two or more conversion tables should be selected is written into an occupied area within a cell. In a switch circuit, the selection information is read and one routing table is selected out of the above described two or more routing tables on the basis of the selection information thus read, and cell routing is thus performed based on information in the selected routing table. Further, in an output interface circuit, selection information contained in the cell is read and one conversion table is selected out of the above described two or more conversion tables on the basis of the selection information thus read, and VPI conversion or VCI conversion is thus executed based on information in the selected conversion table.
    • 一种ATM处理装置中的小区路由方法和装置。 ATM处理装置具有与ATM交换机的地址过滤器相关联的两个或多个路由表,以存储用于指示小区输出的目的地的路由信息​​,以及与用于替换VPI(虚拟路径标识符)的VPI转换电路相关联的两个或更多个转换表, 用于替换VCI(虚拟信道标识符)的VCI转换电路以存储用于指示转换后获得的VPI或VCI的信息。 在输入接口电路中,指示应当选择上述两个或多个路由表和两个或多个转换表中的哪个路由表和转换表的选择信息被写入小区内的占用区域。 在开关电路中,读取选择信息,并且根据这样读取的选择信息,从上述两个或多个路由表中选出一个路由表,并且基于所选择的路由表中的信息执行小区路由 。 此外,在输出接口电路中,读取包含在单元中的选择信息,并且根据这样读取的选择信息从上述两个或更多个转换表中选出一个转换表,并且因此进行VPI转换或VCI转换 基于所选转换表中的信息执行。
    • 66. 发明授权
    • Frame aligner and method and system for control thereof
    • 框架对准器及其控制方法和系统
    • US5271006A
    • 1993-12-14
    • US663956
    • 1991-03-19
    • Yoshihiro AshiTadayuki KannoMasahiro TakatoriHiromi Ueda
    • Yoshihiro AshiTadayuki KannoMasahiro TakatoriHiromi Ueda
    • H04J3/06H04J3/22
    • H04J3/0629
    • A frame aligner and a method and system for control thereof, in which the frame alignment is executed while assuring TSSI (Time Slot Sequence Integrity). In a system for transmitting a plurality of low-speed signals having a frame structure in a high-speed frame, a plurality of candidates for a write start phase for a frame aligner memory are set, and by accessing a common phase memory storing a write start phase shared by low-speed signals requiring phase matching therebetween of all the low-speed signals stored in the high-speed frame, a write start phase is selected from among the candidates for the write start phase for the frame aligner memory.
    • PCT No.PCT / JP90 / 00925 Sec。 371日期1991年3月19日 102(e)1991年3月19日PCT PCT 1990年7月18日PCT公布。 公开号WO91 / 01601 日期1991年2月7日。一种帧对准器及其控制方法和系统,其中在确保TSSI(时隙序列完整性)的同时执行帧对准。 在用于发送具有高速帧中的帧结构的多个低速信号的系统中,设置用于帧对准器存储器的写入开始阶段的多个候选,并且通过访问存储写入的公共相位存储器 低速信号共享的起始相位需要存储在高速帧中的所有低速信号之间的相位匹配,从用于帧对准器存储器的写入开始相位的候选中选择写入开始相位。
    • 67. 发明授权
    • Circuit switching method and apparatus for time division network with
various transmission speeds
    • 具有各种传输速度的时分网络的电路交换方法和装置
    • US5197063A
    • 1993-03-23
    • US641928
    • 1991-01-16
    • Yukio NakanoTadayuki KannoMasahiro TakatoriHiromi Ueda
    • Yukio NakanoTadayuki KannoMasahiro TakatoriHiromi Ueda
    • H04J3/22H04J3/00H04J3/16H04Q11/04
    • H04Q11/04H04J3/1611
    • A circuit switching apparatus and method for time division network with various transmission speeds for time-division multiplexing a plurality of circuits including signals at different transmission speeds, transmitting the same onto an input highway, repeatedly recording the transmitted signals in a data memory in a predetermined order, reading respective recorded signals in a predetermined order onto an output highway. An access unit for reading signals from the data memory has an address control memory for storing circuit switching information, a circuit speed control memory for storing transmission speed information for the respective circuits and an address generating section for generating an address for accessing the data memory on the basis of the circuit switching information and the circuit transmission speed information from those memories.
    • 一种用于具有各种传输速度的时分网络的电路交换装置和方法,用于对包括不同传输速度的信号的多个电路进行时分复用,将其发送到输入公路上,以预定的方式将数据存储器重复地记录发送的信号 以预定顺序将各个记录信号读出到输出高速公路上。 用于从数据存储器读取信号的访问单元具有用于存储电路切换信息的地址控制存储器,用于存储各个电路的传输速度信息的电路速度控制存储器和用于生成访问数据存储器的地址的地址生成部分 电路切换信息的基础和来自这些存储器的电路传输速度信息。
    • 68. 发明申请
    • OPERATION GUARANTEE SYSTEM
    • 操作保证系统
    • US20100182854A1
    • 2010-07-22
    • US12668336
    • 2008-06-27
    • Masahiro Takatori
    • Masahiro Takatori
    • G11C7/00
    • G11C7/1072G11C7/1051G11C7/1066G11C7/222G11C29/022G11C29/023G11C29/028G11C2207/2254
    • An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data signal input from the exterior, and detects the presence or absence of an output error in the decoder circuit. The CPU circuit controls the frequency adjustment circuit and the DQ adjustment circuit to vary a frequency of a clock signal input to an external memory and a delay amount of the data signal. In addition, the CPU circuit acquires a result of detection of the comparison circuit under various conditions. Then, the CPU circuit determines an appropriate frequency of the clock signal input to the external memory based on a relationship between the various conditions and the presence or absence of the output error.
    • 操作保证系统包括解码器电路,比较电路,CPU电路,频率调整电路和DQ调整电路。 比较电路将从解码器电路输入的测试数据信号与从外部输入的期望值数据信号进行比较,并且检测解码器电路中是否存在输出错误。 CPU电路控制频率调整电路和DQ调整电路,以改变输入到外部存储器的时钟信号的频率和数据信号的延迟量。 此外,CPU电路在各种条件下获取比较电路的检测结果。 然后,CPU电路基于各种条件与输出错误的存在或不存在之间的关系来确定输入到外部存储器的时钟信号的适当频率。
    • 70. 发明授权
    • Reception system for replacing transport packets
    • 接收系统,用于替换传输数据包
    • US07304997B2
    • 2007-12-04
    • US11157881
    • 2005-06-21
    • Masahiro TakatoriHidekazu Suzuki
    • Masahiro TakatoriHidekazu Suzuki
    • H04L12/28
    • H04N7/163H04N5/4401H04N5/44543H04N21/4334H04N21/434H04N21/4344H04N21/4345
    • A reception system has a receiving section which receives a transport stream transmitted from a transmission system that produces and transmits the transport stream, the transport stream being produced by multiplexing compression coded contents of a program, and electronic program guide information including program specific information having at least an NIT, a PAT, and a PMT, and service information having at least an SDT and an EIT; a PID designating section which can designate a PID of a packet other than an NIT packet in the electronic program guide information, as a PID of a replace packet (hereinafter, referred to as replace PID); a replace PID storing device which stores the replace PID; an SIT producing section which produces an SIT packet from the service information in the received transport stream; and a packet extracting and replacing section which can replace a replace packet indicated by said replace PID storing device, and the NIT packet with the SIT packet.
    • 接收系统具有:接收部,其接收从传输系统发送的传输流,所述传输流生成并发送传输流,所述传输流是通过复用节目的压缩编码内容产生的,以及包括节目特定信息的电子节目指南信息, 至少NIT,PAT和PMT,以及具有至少SDT和EIT的服务信息; PID指定部,其可以将电子节目指南信息中的NIT分组以外的分组的PID指定为替换分组的PID(以下称为替换PID); 存储替换PID的替换PID存储装置; SIT产生部分,根据所接收的传输流中的服务信息产生SIT分组; 以及可以替换由所述替换PID存储装置指示的替换分组的分组提取和替换部分,以及具有SIT分组的NIT分组。