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61. 发明专利

JPH0151221B2 失效
公开(公告)号：JPH0151221B2
公开(公告)日：1989-11-02
申请号：JP10448381
申请日：1981-07-06
申请人： HITACHI LTD
发明人： MIZOKAWA SADAO , HAMADA TAKUSHI , TOMIZAWA HIROSHI , FUSHIMI HITOSHI
IPC分类号： G06F13/00 , H04L12/433

62. 发明专利

JPS6345935A RESPONSING METHOD FOR LOOP NETWORK 失效
公开(公告)号：JPS6345935A
公开(公告)日：1988-02-26
申请号：JP18780686
申请日：1986-08-12
申请人： HITACHI LTD
发明人： OGAWA HISAO , YASUMOTO SEIICHI , OKADA MASAKAZU , TOMIZAWA HIROSHI , HAMADA TAKUSHI
IPC分类号： H04L12/437
摘要： PURPOSE:To surely inform the state of a reception station to a transmission station while using a required minimum function for multiple address communication by providing an error detection function and modifying the data content if no data is received due to reception buffer busy or the like. CONSTITUTION:A time slot transmission circuit 10, when a transmission request takes place, detects an idle time slot and sends the data. After the end of transmission of time slot, the circulation of the sent time slot is awaited. If the error check pattern (FCS) error is detected in a circulated time slot, a retransmission processing is attained and the reception buffer busy state of the reception station is sent surely to the transmission station. Furthermore, when the reception buffer busy statte continues for a long time in one reception station, the retransmission from the transmission station continues accordingly. In such a case, a prescribed busy supervisory time is provided in the reception state and if the busy state is continued for the time or over, the function of a data rewrite circuit 11 is blocked to return the cyclic data to the transmission station normally.

63. 发明专利

JPS6318843A RESPONSE METHOD FOR MULTIPLE ADDRESS COMMUNICATION 失效
公开(公告)号：JPS6318843A
公开(公告)日：1988-01-26
申请号：JP16198786
申请日：1986-07-11
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： MUTO KOJI , YASUMOTO SEIICHI , OKADA MASAKAZU , TOMIZAWA HIROSHI
摘要： PURPOSE:To ensure the response of multiple address communication by providing an address recognition field writing whether or not each receiving station recognizes a sender address in its frame to be its own sender address and a buffer field writing whether or not its own reception buffer is busy in a transmission frame. CONSTITUTION:Data of frame form constituted by a HDLC control circuit 5 is decided in itself whether or not the data is addressed to the master station and also decides whether or not a reception buffer is busy in this case, the results C, D of decision are sent to the reception state control circuit 9. Further, the result of AR and BVUF fields in the reception frame is extracted and sent as signals A, B to the reception state control circuit 9. When it is decided to be the reseption station, the received data is stored in a buffer area of a RAM 8 via a bus 1 and the circuit 5, when the end flag F of the HDLC frame is received, an intrruption signal 10 to a microprocessor 6 is set to apply communication.

64. 发明专利

JPS62163436A DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPS62163436A
公开(公告)日：1987-07-20
申请号：JP345086
申请日：1986-01-13
申请人： HITACHI LTD
发明人： TOMIZAWA HIROSHI , YASUMOTO SEIICHI , OKADA MASAKAZU , TAKAHASHI MASAHIRO , HAMADA TAKUSHI
摘要： PURPOSE:To utilize effectively a time slot by providing the time slot for sending in the same node station to a transmission frame flowing to a loop transmission line. CONSTITUTION:Plural computers and input/output equipments in respective node stations are connected to the loop transmission line 1 via adaptors 25, 25... and a bus 23. In sending the adaptors in the same station, an adaptor #2 acquiring the transmission right receives an idle slot in the data transmission time slot for the data sending in the same station in the frame sent to the transmission line 1, transmission data is superimposed on the said slot and sent to the bus 24 connecting the adaptors in the same station. A data reception adaptor #1 receives the time slot addressed to the own device from the bus 24, the said slot is made idle and sent to the bus 23. Then in sending data in the same station, the occupancy of the transmission line 1 is not required and the time slot is utilized effectively.

65. 发明专利

JPS61228749A ERROR CONTROL SYSTEM IN MULTIPLE ADDRESS COMMUNICATION SYSTEM 失效
公开(公告)号：JPS61228749A
公开(公告)日：1986-10-11
申请号：JP6941185
申请日：1985-04-02
申请人： HITACHI LTD
发明人： TOMIZAWA HIROSHI , YASUMOTO SEIICHI , OKADA MASAKAZU , ONUKI TAKESHI
IPC分类号： H04L1/00
摘要： PURPOSE:To save the memory capacity and to improve the efficiency of reception processing by providing a function applying data retransmission processing after a data transmission controller sending the data and detecting an error in a cyclic data gives simultaneous command of ineffective handling of the data immediately. CONSTITUTION:When a data transmission controller 1 sends a data to other device, an HDLC control circuit 6 fetches the data in a RAM 10, converts the data into a serial data and after a flag F, a transmission destination station address DA, a control command C, and a transmission destination address SA are added, the result is sent from a transmitter 4 via an MPX 13. When the data is circulated in a loop and enters a receiver 3, the data is subject to cyclic check at the HDLC control 3 and whether or not an error exists is checked, and when an error exists, an interruption signal 16 reports the error detection to an MPU 8. When the report of the error is received, the MPU 8 sends an ABORT pattern via an HDLC control circuit. The transmitter detecting the ABORT pattern makes the data received before ineffective unconditionally.

66. 发明专利

JPS59136850A Selection and control method of microprogram memory 失效
标题翻译：微波存储器的选择与控制方法
公开(公告)号：JPS59136850A
公开(公告)日：1984-08-06
申请号：JP987983
申请日：1983-01-26
申请人： Hitachi Ltd
发明人： TOMIZAWA HIROSHI , YASUMOTO SEIICHI , OKADA MASAKAZU , OOHAYASHI MASANAO
IPC分类号： G06F9/06 , G06F9/22 , G06F9/26
CPC分类号： G06F9/267
摘要： PURPOSE:To attain the addition or extension of memories with no change or with the minimum necessary change of both hardware and software, by storing a microprogram after dividing it previously into two systems and selecting these memories in terms of hardware. CONSTITUTION:A memory is divided into memories 3A and 3B. An instruction JSR A which jumps to a subroutine of the head address A within the memory 3B is executed while the memory 3A is selected to execute a microprogram. Then the 3B is selected in place of the 3A. In this case, a returned address, i.e., the address next to the instruction JSR A is set at the stack of an address control part 2. Therefore, the 3A is selected again if the as instruction return subroutine is executed after the subroutine corresponding to the address A. Thus the instruction corresponding to the address next to the instruction JSR A is executed. In such a way, both addition and extension of a memory are possible with high efficiency by using a double system memory.
摘要翻译：目的：通过在先前将其分割成两个系统并在硬件上选择这些存储器之后存储微程序，来实现无变化或硬件和软件的最小必要更改的存储器的添加或扩展。构成：存储器被分成存储器3A和3B。在选择存储器3A以执行微程序的同时，执行跳转到存储器3B内的头地址A的子程序的指令JSR A。然后选择3B代替3A。在这种情况下，返回的地址，即指令JSR A旁边的地址被设置在地址控制部分2的堆栈处。因此，如果在对应于子程序的子程序之后执行as指令返回子程序，则再次选择3A 地址A.因此，执行与指令JSR A旁边的地址相对应的指令。以这种方式，通过使用双系统存储器，可以高效率地增加和扩展存储器。

67. 发明专利

JPS5983435A FAILURE RETRIEVING METHOD OF LOOP TRANSMISSION LINE 失效
公开(公告)号：JPS5983435A
公开(公告)日：1984-05-14
申请号：JP19332582
申请日：1982-11-05
申请人： HITACHI LTD
发明人： TOMIZAWA HIROSHI , MIZOKAWA SADAO , HAMADA TAKUSHI , OKADA MASAKAZU , OONUKI TAKESHI
IPC分类号： H04L12/437
摘要： PURPOSE:To retrieve plural failed parts, by outputting a retrieval command to each station via a sound transmission line in the lump when a transmission failure is detected and outputting a monitor signal to the failed transmission line from the station receiving it. CONSTITUTION:A control station CST is classified roughly into a microcomputer part 100 comprising a microprocessor 17, an exclusive memory incorporating a microprogram, a memory 19 such as a data buffer, an internal bus 20, a communication control LSI21, and a conventional input control LSI22, and into a transmission section comprising a modulation circuit 26 and a demodulation circuit 27 and the like. The transmission data is modulated by a modulating circuit 26 and inputted to transmission circuits 33, 36 via multiplexers 31, 32 in response to the content of selecting signals SA, SB from a control circuit 29. The station CST is provided with a connection command generating circuit 23 and a monitor signal generating circuit 24.

68. 发明专利

JPS5950639A Method for detecting restoration of failure in loop data transmission system 失效
标题翻译：检测循环数据传输系统中故障恢复的方法
公开(公告)号：JPS5950639A
公开(公告)日：1984-03-23
申请号：JP15956382
申请日：1982-09-16
申请人： Hitachi Ltd
发明人： OONUKI TAKESHI , TAKAHASHI MASAHIRO , HAMADA TAKUSHI , MIZOKAWA SADAO , FUSHIMI HITOSHI , YASUMOTO SEIICHI , OKADA MASAKAZU , TOMIZAWA HIROSHI
IPC分类号： H04L12/437
CPC分类号： H04L12/437
摘要： PURPOSE:To detect automatically the state of restoration in a failed section, by transmitting a monitor signal to a signal intermitting section by a loop back terminal station and receiving the monitor signal transmitted from the loop back terminal station of opposite party via a signal relay section. CONSTITUTION:When a signal interruption takes place on transmission lines 3d, 4d, a transmission controller 2c connects a signal on a transmission line 4c to a transmission line 3c and a transmission controller 2d connects a signal from a transmission line 3e to a transmission line 4e, respectively, and a monitor controller 1 connects a signal from a transmission line 3a to a transmission line 3h and connects a signal from a transmission line 4h to a transmission line 4a, respectively to constitute the loop back. Monitor signal generating circuits 24c, d keep to transmit the monitor signal to the signal interruption sections 3d, 4d from the controllers 2c, 2d. Further, detecting circuits 25c, 28d monitor whether the monitor signal transmitted from the opposite party is transmitted on the transmission lines 3d, 4d. When the transmission lines 3d, 4d are restored, the circuit 25c, 28d detect the transmission of the monitor signal and recognizes that the signal interruption section is restored.
摘要翻译：目的：自动检测故障部分的恢复状态，通过环回终端将监控信号发送到信号中断部分，并通过信号中继部分接收从对方的环回终端发送的监视信号。构成：当在传输线3d，4d上发生信号中断时，传输控制器2c将传输线路4c上的信号连接到传输线路3c，并且传输控制器2d将来自传输线路3e的信号连接到传输线路4e 并且监视器控制器1将来自传输线3a的信号连接到传输线3h，并将来自传输线4h的信号分别连接到传输线4a以构成回路。监视信号发生电路24c，d保持将监视信号从控制器2c，2d发送到信号中断部分3d，4d。此外，检测电路25c，28d监视在传输线3d，4d上是否发送从对方发送的监视信号。当传输线3d，4d恢复时，电路25c，28d检测监视信号的传输并识别信号中断部分恢复。

69. 发明专利

JPS586637A CIRCUIT CONTROLLING METHOD OF LOOP TYPE DATA WAY SYSTEM 失效
公开(公告)号：JPS586637A
公开(公告)日：1983-01-14
申请号：JP10448381
申请日：1981-07-06
申请人： HITACHI LTD
发明人： MIZOKAWA SADAO , HAMADA TAKUSHI , TOMIZAWA HIROSHI , FUSHIMI HITOSHI
IPC分类号： G06F13/00 , H04L12/433
摘要： PURPOSE:To allow a station (ST), which has an occupation request, in a loop type data way system to write a declaration pattern in advance and to acquire the right to occupy, by composing a frame for inquiring the occupation request of another station ST of an inquiry part and a declaration part. CONSTITUTION:A receiving circuit 9 receives data from an up circuit, and the data is synchronized by a synchronizing circuit 2 and sent out of a transmitting circuit 10 to a down circuit. The received data is inputted to a shift register 22 simultaneously and a polling (POL) pattern when present is detected by a comparator 24; when this ST sends a request to send, the declaration (RSV) pattern of the right to occupy is outputted from a circuit 32 by a signal 7e from a control circuit 29 and transmitted. The received data, on the other hand, is further shifted by a register 23 and when a comparator 25 detects the presence of the RSV pattern for showing that occupation is completed after the POL pattern, it is judged that the right to occupy could not be obtained, and a repeating mode is set; when the RSV pattern is not found, it is judged that the right to occupy is obtained, and a transmission mode is set, thereby sending the data.

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