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    • 68. 发明授权
    • Data reading circuit for semiconductor memory device
    • 半导体存储器件的数据读取电路
    • US4843595A
    • 1989-06-27
    • US4950
    • 1987-01-20
    • Atsushi Suzuki
    • Atsushi Suzuki
    • G11C11/41G11C7/06G11C7/10
    • G11C7/1057G11C7/062G11C7/1048G11C7/1051
    • A data reading circuit for a semiconductor memory device includes: a first input terminal and a second input terminal each receiving complementary signals. A first and a second current mirror type sense amplifiers, each including a reference node, an output terminal, a first transistor connected with the reference node, and a second transitor connected with the output terminal. A gate of the first transitor of the first current mirror type sense amplifier and a gate of the second transistor of the second current mirror type sense amplifier are connected to the first input terminal. A gate of the second transistor of the first current mirror type sense amplifier and a gate of the first transitor of the second current mirror type sense amplifier are connected to a second input terminal. The data reading circuit further includes a short-circuiting transistor connected between the reference nodes of both the first and the second current mirror type sense amplifiers. The first short-circuiting transistor is able to conduct therethrough temporarily by receiving a clock signal at a gate.
    • 一种用于半导体存储器件的数据读取电路包括:第一输入端和第二输入端,每个接收互补信号。 第一和第二电流镜型读出放大器,每个包括参考节点,输出端子,与参考节点连接的第一晶体管,以及与输出端子连接的第二转换器。 第一电流镜型读出放大器的第一输入端的栅极和第二电流镜型读出放大器的第二晶体管的栅极连接到第一输入端。 第一电流镜式读出放大器的第二晶体管的栅极和第二电流镜型读出放大器的第一晶体管的栅极连接到第二输入端。 数据读取电路还包括连接在第一和第二电流镜型读出放大器的参考节点之间的短路晶体管。 第一短路晶体管能够通过在栅极处接收时钟信号而临时导通。