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61. 发明申请

US20100306615A1 Receiving Apparatus, Receiving Method and Program, and Receiving System 有权
标题翻译：接收装置，接收方法和程序以及接收系统
公开(公告)号：US20100306615A1
公开(公告)日：2010-12-02
申请号：US12783120
申请日：2010-05-19
申请人： Naomichi KISHIMOTO , Hideyuki Matsumoto , Toshiyuki Miyauchi , Yuichi Mizutani
发明人： Naomichi KISHIMOTO , Hideyuki Matsumoto , Toshiyuki Miyauchi , Yuichi Mizutani
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1111 , H03M13/1128 , H03M13/1165 , H03M13/3715 , H03M13/6502
摘要： Disclosed herein is a receiving apparatus, including: a decoding section configured to receive and decode an low density parity check code; and a decoding control section configured to control a frequency of the decoding on the basis of conditional information that is an index indicative of a communication condition that influences power consumption in the decoding section.
摘要翻译：这里公开了一种接收装置，包括：解码部分，被配置为接收和解码低密度奇偶校验码; 以及解码控制部分，被配置为基于作为指示在解码部分中影响功耗的通信条件的索引的条件信息来控制解码的频率。

62. 发明申请

US20070104296A1 Viterbi decoding apparatus 有权
标题翻译：维特比解码装置
公开(公告)号：US20070104296A1
公开(公告)日：2007-05-10
申请号：US11473126
申请日：2006-06-23
申请人： Toshiyuki Miyauchi , Yuichi Mizutani
发明人： Toshiyuki Miyauchi , Yuichi Mizutani
IPC分类号： H03D1/00 , H03M13/03
CPC分类号： H03M13/4176 , H03M13/4169 , H03M13/6502
摘要： The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.
摘要翻译：本发明可以减少跟踪时的功耗。本发明提供了一种用于对卷积码进行解码的维特比解码装置，其包括路径存储单元，该路径存储单元存储朝向卷积码的各自转换状态的两条路径之一作为多个连续时间点的选定路径，跟踪单元其沿着反向时间方向跟踪存储在路径存储器单元中的所选择的路径，从而在各个时间点对每个时间点进行解码，每个时间点在预定的跳闸周期之前，以及控制单元，路径存储单元，其中，路径存储单元具有被设计为存储在各个时间点处各自的过渡状态的所选择的路径的存储区域，所述存储区域被划分为从过渡状态的最低阶的子区域，每个子区域对应于预定位数，并且可以针对每个子区域停止读取数据，并且控制单元指定没有选择的路径n的子区域在各个时间点读取数据，以停止从指定的子区域读取数据。

63. 发明授权

US07180968B2 Soft-output decoding 失效
标题翻译：软输出解码
公开(公告)号：US07180968B2
公开(公告)日：2007-02-20
申请号：US10111724
申请日：2001-08-31
申请人： Toshiyuki Miyauchi , Kouhei Yamamoto
发明人： Toshiyuki Miyauchi , Kouhei Yamamoto
IPC分类号： H03D1/00
CPC分类号： H03M13/2957 , H03M13/27 , H03M13/2903 , H03M13/6566
摘要： To appropriately express an erasure position of a code by a small-scale, simple-structured circuit, a soft-output decoding circuit (90) in each element decoder includes a received value and a priori probability information selection circuit (154) to select an input to-be-decoded received value TSR and extrinsic information or interleaved data TEXT, whichever is necessary for soft-output decoding. Based on inner erasure position information IERS supplied from an inner erasure information generating circuit (152), the received value and a priori probability information selection circuit (154) replaces a position where no coded output exists due to puncture or the like with a symbol whose likelihood is “0”. That is, the received value and a priori probability information selection circuit (154) outputs information which assures a probability in which a bit corresponding to a position where there is no coded output is “0” or “1” to be “½”.
摘要翻译：为了通过小规模，简单的结构化电路适当地表示代码的擦除位置，每个元件解码器中的软输出解码电路（90）包括接收值和先验概率信息选择电路（154），以选择输入待解码的接收值TSR和外部信息或交织数据TEXT，以软输出解码为准。基于从内部擦除信息生成电路（152）提供的内部擦除位置信息IERS，接收到的值和先验概率信息选择电路（154）用一个符号代替由于穿孔等而不存在编码输出的位置，可能性为“0”。也就是说，接收的值和先验概率信息选择电路（154）输出确定与没有编码输出的位置相对应的位为“0”或“1”的概率的信息。

64. 发明授权

US06826722B2 Method and apparatus for reproducing data and method and apparatus for recording and/or reproducing data 失效
标题翻译：用于再现数据的方法和装置，用于记录和/或再现数据的方法和装置
公开(公告)号：US06826722B2
公开(公告)日：2004-11-30
申请号：US09814280
申请日：2001-03-21
申请人： Toshiyuki Miyauchi , Masayuki Hattori , Jun Murayama
发明人： Toshiyuki Miyauchi , Masayuki Hattori , Jun Murayama
IPC分类号： G06F1100
CPC分类号： G11B20/10 , H03M13/39
摘要： A magnetic recording and/or reproducing apparatus in which the decoding error rate is to be lowered through realization of the high-performance encoding and the high efficiently decoding. To this end, a magnetic recording and/or reproducing apparatus 50 includes, in its recording system, an error correction coder 51 for error correction encoding input data, an interleaver 52 for interleaving data supplied from the error correction coder 51 for re-arraying the data sequence, a modulation encoder 53 for modulation encoding the data from the interleaver 52 in a predetermined fashion and an interleaver 54 for interleaving the data from the modulation encoder 53 for re-arraying the data sequence. The magnetic recording and/or reproducing apparatus 50 also includes, in its reproduction system, a channel, modulation and error correction turbo decoder 64 formed by concatenation of an error correction soft decoder and a modulation decoder for decoding the input data with the interposition of two deinterleavers and two interleavers.
摘要翻译：一种通过实现高性能编码和高效解码来降低解码错误率的磁记录和/或再现装置。为此，磁记录和/或再现装置50在其记录系统中包括用于对输入数据进行纠错编码的纠错编码器51，用于交错从纠错编码器51提供的数据的交织器52用于重新排列数据序列，用于以预定方式对来自交织器52的数据进行调制编码的调制编码器53和用于对来自调制编码器53的数据进行交织以重新排列数据序列的交织器54。磁记录和/或再现装置50在其再现系统中还包括通道，调制和纠错turbo解码器64，其通过错误校正软解码器和调制解码器的级联形成，该调制解码器用于对输入数据进行解码以插入两个去交织器和两个交织器。

65. 发明授权

US06748034B2 Viterbi decoding apparatus and viterbi decoding method 失效
标题翻译：维特比解码装置和维特比解码方法
公开(公告)号：US06748034B2
公开(公告)日：2004-06-08
申请号：US09215452
申请日：1998-12-17
申请人： Masayuki Hattori , Toshiyuki Miyauchi
发明人： Masayuki Hattori , Toshiyuki Miyauchi
IPC分类号： H04L2706
CPC分类号： H03M13/6583 , H03M13/4107 , H03M13/4123 , H03M13/4161 , H03M13/4176
摘要： A register train is provided in addition to a train of memory cells as many as a cut length which are arranged in correspondence to each state. Outputs of selectors at respective stages in the register train corresponding to state 00 are inputted to a register (1021) in the register train and selectors. Outputs of the registers at the front stages are inputted to those three selectors, respectively. The three selectors switch outputs to the post stages in accordance with a control by a control circuit when a reception word is terminated and in the other cases. Thus, when the reception word is terminated, information stored in the register train is transferred as it is. By such an operation, a path which reaches state 00 can be decoded when a reception word is terminated.
摘要翻译：除了与每个状态相对应地布置有与切割长度一样多的存储单元串之外，还提供了一个寄存器列。对应于状态00的寄存器列中的各个级的选择器的输出被输入到寄存器列和选择器中的寄存器（1021）。前级寄存器的输出分别输入到这三个选择器。当接收字终止时，根据控制电路的控制，在其他情况下，三个选择器将输出切换到后级。因此，当接收字终止时，存储在寄存器列中的信息被原样传送。通过这样的操作，当接收字终止时，可以对达到状态00的路径进行解码。

66. 发明授权

US06525680B2 Decoder and decoding method 失效
标题翻译：解码和解码方法
公开(公告)号：US06525680B2
公开(公告)日：2003-02-25
申请号：US09876701
申请日：2001-06-07
申请人： Kouhei Yamamoto , Toshiyuki Miyauchi
发明人： Kouhei Yamamoto , Toshiyuki Miyauchi
IPC分类号： H03M700
CPC分类号： H03M13/3911 , H03M13/3922 , H03M13/3927
摘要： A decoder has a reduced circuit dimension that does not adversely affect the decoding performance of the circuit. The decoder includes an addition/comparison/selection circuit added to give the log likelihood and adapted to compute a correction item expressed in a one-dimensional function relative to a variable and add a predetermined value to the correction term in order to provide a unified symbol for identifying the positiveness or negativeness of the log likelihood for the purpose of computing the log likelihood.
摘要翻译：解码器具有减小的电路尺寸，其不会不利地影响电路的解码性能。该解码器包括一个加法/比较/选择电路，其被添加以产生对数似然性，并适于计算相对于变量表示的一维函数的校正项，并将一个预定值加到校正项上，以便提供统一符号用于识别用于计算对数似然度的对数似然性的积极性或消极性。

67. 发明授权

US06192084B1 Soft output decoding apparatus and method for convolutional code 有权
标题翻译：软输出解码装置及卷积码的方法
公开(公告)号：US06192084B1
公开(公告)日：2001-02-20
申请号：US09318584
申请日：1999-05-25
申请人： Toshiyuki Miyauchi , Masayuki Hattori
发明人： Toshiyuki Miyauchi , Masayuki Hattori
IPC分类号： H04L2302
CPC分类号： H03M13/3972 , H03M13/3905 , H03M13/3911 , H03M13/3922 , H03M13/3927 , H03M13/6566
摘要： A soft output decoding method and apparatus are provided for provided convolutional codes. After computing the number of states times I&bgr; (&bgr;t˜&bgr;t−D+1) for a truncated length, the soft output outside the truncated length is sequentially computed, as next following I&bgr; (&bgr;t−D˜&bgr;t−2D+1) outside the next following truncated length is computed, at the same time as I&bgr; of the next truncated length is sequentially computed. In this manner, a decoder performs computation of I&bgr; within the truncated length and computation of I&bgr; retrogressive by not less than the truncated length, in parallel processing, as a result of which the computation of I&bgr; per clock is the number of states x2. This apparatus and method thereby reduces the volume of computation and expedites the decoding.
摘要翻译：提供了一种软输出解码方法和装置，用于提供卷积码。在计算截断长度的Ibeta（betat〜betat-D + 1）的状态数之后，依次计算截断长度之外的软输出，如下面的Ibeta（betat-D〜betat-2D + 1）之外的计算下一个截断长度后的下一个截断长度的Ibeta，同时依次计算下一个截断长度的Ibeta。以这种方式，解码器在并行处理中执行截断长度内的Ibeta的计算和倒数长度的Ibeta倒排计算，其结果是每个时钟Ibeta的计算是状态数x2。该装置和方法因此减少了计算量并加快了解码。

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