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61. 发明申请

US20130346728A1 Optimizing Performance Of Instructions Based On Sequence Detection Or Information Associated With The Instructions 有权
标题翻译：基于序列检测或与指令相关的信息优化指令性能
公开(公告)号：US20130346728A1
公开(公告)日：2013-12-26
申请号：US14012344
申请日：2013-08-28
申请人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
发明人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/325 , G06F9/3855 , G06F9/3857
摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一个指令解码器，其可以接收输入指令和路径选择信号，并且响应于路径选择信号将输入指令解码为第一指令代码或第二指令代码。代表相同输入指令的两个不同的指令代码可以被执行单元用于执行针对不同数据长度优化的操作。描述和要求保护其他实施例。

62. 发明授权

US08566492B2 Posting interrupts to virtual processors 有权
公开(公告)号：US08566492B2
公开(公告)日：2013-10-22
申请号：US12650581
申请日：2009-12-31
申请人： Rajesh Sankaran Madukkarumukumana , Gilbert Neiger , Ohad Falik , Sridhar Muthrasanallur , Gideon Gerzon
发明人： Rajesh Sankaran Madukkarumukumana , Gilbert Neiger , Ohad Falik , Sridhar Muthrasanallur , Gideon Gerzon
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/4812
摘要： Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

63. 发明申请

US20130132683A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130132683A1
公开(公告)日：2013-05-23
申请号：US13713614
申请日：2012-12-13
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus forenhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

64. 发明授权

US08099523B2 PCI express enhancements and extensions including transactions having prefetch parameters 有权
标题翻译： PCI Express增强和扩展，包括具有预取参数的事务
公开(公告)号：US08099523B2
公开(公告)日：2012-01-17
申请号：US13073219
申请日：2011-03-28
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Abraham Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Abraham Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F3/00
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

65. 发明申请

US20110238974A1 METHODS AND APPARATUS TO IMPROVE TURBO PERFORMANCE FOR EVENTS HANDLING 审中-公开
标题翻译：提高事件处理的涡轮性能的方法和装置
公开(公告)号：US20110238974A1
公开(公告)日：2011-09-29
申请号：US13156268
申请日：2011-06-08
申请人： Ryan D. Wells , Ohad Falik , Jose P. Allarey , Mary Jean Allarey
发明人： Ryan D. Wells , Ohad Falik , Jose P. Allarey , Mary Jean Allarey
IPC分类号： G06F9/00
CPC分类号： G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/3237 , G06F1/3243 , G06F1/3246 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F1/3296 , G06F9/5027 , G06F9/5094 , G06F2209/501 , Y02D10/126 , Y02D10/17 , Y02D10/171 , Y02D10/22 , Y02D10/26 , Y02D50/20
摘要： Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.
摘要翻译：介绍了一种改善事件处理性能的装置的实施例。在一个实施例中，该装置包括多个处理元件和任务布线逻辑。如果至少一个处理元件处于turbo模式，则任务路由逻辑至少基于性能损失的比较来选择用于执行任务的处理元件。

66. 发明申请

US20110238882A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 有权
公开(公告)号：US20110238882A1
公开(公告)日：2011-09-29
申请号：US13073149
申请日：2011-03-28
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/14
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

67. 发明申请

US20110138388A1 METHODS AND APPARATUSES TO IMPROVE TURBO PERFORMANCE FOR EVENTS HANDLING 有权
标题翻译：提高事件处理的涡轮性能的方法和装置
公开(公告)号：US20110138388A1
公开(公告)日：2011-06-09
申请号：US12630438
申请日：2009-12-03
申请人： Ryan D. Wells , Ohad Falik , Jose P. Allarey , Mary Jean Allarey
发明人： Ryan D. Wells , Ohad Falik , Jose P. Allarey , Mary Jean Allarey
IPC分类号： G06F9/46
CPC分类号： G06F1/324 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/3234 , G06F1/3237 , G06F1/3243 , G06F1/3246 , G06F1/3287 , G06F1/329 , G06F1/3293 , G06F1/3296 , G06F9/5027 , G06F9/5094 , G06F2209/501 , Y02D10/126 , Y02D10/17 , Y02D10/171 , Y02D10/22 , Y02D10/26 , Y02D50/20
摘要： Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.
摘要翻译：介绍了一种改善事件处理性能的装置的实施例。在一个实施例中，该装置包括多个处理元件和任务布线逻辑。如果至少一个处理元件处于turbo模式，则任务路由逻辑至少基于性能损失的比较来选择用于执行任务的处理元件。

68. 发明申请

US20110072164A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 有权
公开(公告)号：US20110072164A1
公开(公告)日：2011-03-24
申请号：US12883781
申请日：2010-09-16
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F3/00 , G06F13/42
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

69. 发明授权

US07598722B1 Method and apparatus for sensing temperature 失效
标题翻译：检测温度的方法和装置
公开(公告)号：US07598722B1
公开(公告)日：2009-10-06
申请号：US11589846
申请日：2006-10-30
申请人： Ohad Falik
发明人： Ohad Falik
IPC分类号： G01N27/00 , G01K7/00 , H03K5/22 , H01L35/00
CPC分类号： G01K15/00 , G01K7/01
摘要： Method and system for periodically measuring the junction temperature of a semiconductor device. The junction exited by at least two sequential predetermined currents of different magnitudes. The voltage response of the junction to the at least two currents is measured and the temperature of the junction is calculated, while substantially canceling ohmic effects, by using the voltage response and a correction factor obtained by periodically. Whenever desired, the junction is exited by a set of at least four sequential different currents having known ratios. The voltage response to the set is measured and the correction factor is calculated by using each voltage response to the set.
摘要翻译：用于周期性测量半导体器件的结温的方法和系统。接点由不同幅度的至少两个顺序的预定电流退出。测量结到至少两个电流的电压响应，并且通过使用电压响应和通过周期性获得的校正因子来计算结点的温度，同时基本上消除欧姆效应。无论何时，通过一组具有已知比例的至少四个顺序的不同电流退出结。测量对该组的电压响应，并通过使用对该组的每个电压响应来计算校正因子。

70. 发明申请

US20080215822A1 PCI Express Enhancements and Extensions 有权
标题翻译： PCI Express增强功能和扩展
公开(公告)号：US20080215822A1
公开(公告)日：2008-09-04
申请号：US11933178
申请日：2007-10-31
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

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