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61. 发明授权

US06418060B1 Method of programming and erasing non-volatile memory cells 失效
标题翻译：编程和擦除非易失性存储单元的方法
公开(公告)号：US06418060B1
公开(公告)日：2002-07-09
申请号：US09683463
申请日：2002-01-03
申请人： Ching-Sung Yang , Ching-Hsiang Hsu
发明人： Ching-Sung Yang , Ching-Hsiang Hsu
IPC分类号： G11C1600
CPC分类号： H01L29/792 , G11C16/10 , G11C16/14 , H01L27/115
摘要： A method of selectively programming an individual memory cell of a non-volatile memory array. The non-volatile memory array is an array of memory cells. Each memory cell is made up of an ONO gate built on a substrate, which also acts as a well. On one side of the gate is a diffusion drain encompassed by a localized well region set in the well. On the other side of the gate is a diffusion source set in the well. When operated, appropriate voltages are applied to the source, the gate, the drain, and the localized well region to program or erase the non-volatile memory. The designed localized well region prevents an induction current in the unselected gates of the array, allowing for better selectivity and performance.
摘要翻译：一种选择性地编程非易失性存储器阵列的单个存储单元的方法。非易失性存储器阵列是存储器单元阵列。每个存储单元由构建在基板上的ONO门组成，其也用作阱。在门的一侧是由井中设置的局部井区域包围的扩散漏斗。在门的另一边是设置在井中的扩散源。当操作时，向源极，栅极，漏极和局部阱区域施加适当的电压以编程或擦除非易失性存储器。设计的局部阱区域可防止阵列未选择的栅极中的感应电流，从而实现更好的选择性和性能。

62. 发明申请

US20130121079A1 NOR FLAH MEMORY CELL AND STRUCTURE THEREOF 审中-公开
公开(公告)号：US20130121079A1
公开(公告)日：2013-05-16
申请号：US13295102
申请日：2011-11-14
申请人： Meng-Yi Wu , Ching-Sung Yang
发明人： Meng-Yi Wu , Ching-Sung Yang
IPC分类号： G11C16/04 , H01L29/78
CPC分类号： H01L29/792 , G11C16/0433 , H01L27/1157 , H01L29/518
摘要： The present invention provides a NOR flash memory cell. The NOR flash memory cell includes a first transistor, a second transistor and at least one third transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control terminal used to receive a word line signal and the first terminal used to receive a bit line signal. A gate of the first transistor comprises a silicon-rich nitride layer and an oxide layer, wherein the silicon-rich nitride layer is buried in the oxide layer. A control terminal of the second transistor used to receive a read signal. A second terminal of the second transistor used to transport a source line signal according to the read signal. The third transistor coupled between the first transistor and the bit line signal, and a control terminal of the third transistor receives a midway control signal.
摘要翻译：本发明提供了一种NOR闪存单元。 NOR闪存单元包括第一晶体管，第二晶体管和至少一个第三晶体管。第一晶体管具有控制端子，第一端子和第二端子。用于接收字线信号的控制终端和用于接收位线信号的第一终端。第一晶体管的栅极包括富含硅的氮化物层和氧化物层，其中富含硅的氮化物层被掩埋在氧化物层中。用于接收读取信号的第二晶体管的控制端。第二晶体管的第二端子用于根据读取信号传输源极线信号。耦合在第一晶体管和位线信号之间的第三晶体管，以及第三晶体管的控制端子接收中途控制信号。

63. 发明申请

US20090235328A1 DATA ACCESSING SYSTEM 审中-公开
标题翻译：数据访问系统
公开(公告)号：US20090235328A1
公开(公告)日：2009-09-17
申请号：US12258428
申请日：2008-10-26
申请人： Tung-Cheng Kuo , Ching-Sung Yang , Ruei-Ling Lin , Cheng-Jye Liu
发明人： Tung-Cheng Kuo , Ching-Sung Yang , Ruei-Ling Lin , Cheng-Jye Liu
IPC分类号： G06F21/00
CPC分类号： G06F21/79
摘要： A data accessing system includes a host and a storage device. The host has a security setup function and includes a first identity code storage block. The host executes the security setup function to set a first identity code according to a second identity code, and the second identity code is stored into the first identity code storage block. The storage device has a security check function and includes a second identity code storage block to store the second identity code, and the storage device executes the security check function to determine if the host is allowed to access the storage device according to the first identity code.
摘要翻译：数据访问系统包括主机和存储设备。主机具有安全设置功能，并且包括第一身份码存储块。主机执行安全设置功能以根据第二身份码设置第一身份码，并且将第二身份码存储到第一身份码存储块中。存储装置具有安全检查功能，并且包括存储第二身份码的第二身份码存储块，并且存储装置执行安全检查功能，以确定主机是否被允许根据第一身份码访问存储装置。

64. 发明授权

US07335559B2 Fabricating method of non-volatile memory 有权
标题翻译：非易失性存储器的制作方法
公开(公告)号：US07335559B2
公开(公告)日：2008-02-26
申请号：US11778655
申请日：2007-07-17
申请人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
发明人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
IPC分类号： H01L21/336
CPC分类号： G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.
摘要翻译：提供非易失性存储器。衬底在其中具有至少两个隔离结构以限定有效区域。一个井位于基板中。浅掺杂区域位于井中。至少两个堆叠的栅极结构位于衬底上。袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。辅助栅极层位于堆叠栅极结构之间的衬底上。栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

65. 发明申请

US20070085124A1 NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法及其工作方法
公开(公告)号：US20070085124A1
公开(公告)日：2007-04-19
申请号：US11558747
申请日：2006-11-10
申请人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
发明人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
IPC分类号： H01L29/94 , H01L21/20 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/115 , H01L21/28282 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926 , Y10S438/954
摘要： A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate, The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.
摘要翻译：提供了具有基板，n型阱，p型阱，控制栅极，复合电介质层，源极区域和漏极区域的非易失性存储器件。在衬底中形成沟槽。 n型阱形成在衬底中，p型阱形成在n型阱上方的衬底中。 p型阱和n型阱的结点高于沟槽的底部。突出基板表面的控制栅极形成在沟槽的侧壁上。复合介质层形成在控制栅极和衬底之间。复合介电层包括电荷捕获层。源极区域和漏极区域分别形成在沟槽底部的衬底中，分别在控制栅极的侧面旁边。

66. 发明申请

US20070040197A1 NON-VOLATILE MEMORY, MANUFACTURING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器，制造方法及其工作方法
公开(公告)号：US20070040197A1
公开(公告)日：2007-02-22
申请号：US11307871
申请日：2006-02-26
申请人： Ching-Sung Yang , Wei-Zhe Wong
发明人： Ching-Sung Yang , Wei-Zhe Wong
IPC分类号： H01L29/94
CPC分类号： H01L29/7887 , G11C16/0458 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/7923
摘要： A non-volatile memory including a memory unit, a first bit line and a second bit line is provided. The memory unit includes a first doped region, a second doped region, a first memory cell, a select gate structure, and a second memory cell. The first doped region and the second doped region are formed in the substrate. The first memory cell, the select gate structure, and the second memory cell are formed between the first doped region and the second doped region on the substrate. The first memory cell is adjacent to the first doped region and the second memory is adjacent to the second doped region. The first bit line and the second bit line are formed on the substrate in parallel. The first doped region is electrically connected to the first bit line, and the second doped region is electrically connected to the second bit line.
摘要翻译：提供包括存储单元，第一位线和第二位线的非易失性存储器。存储单元包括第一掺杂区，第二掺杂区，第一存储单元，选择门结构和第二存储单元。在衬底中形成第一掺杂区和第二掺杂区。第一存储单元，选择栅结构和第二存储单元形成在衬底上的第一掺杂区和第二掺杂区之间。第一存储单元与第一掺杂区相邻，第二存储器与第二掺杂区相邻。第一位线和第二位线平行地形成在基板上。第一掺杂区域电连接到第一位线，并且第二掺杂区域电连接到第二位线。

67. 发明申请

US20060289925A1 NON-VOLATILE MEMORY, MANUFACTURING METHOD AND OPERATING METHOD THEREOF 有权
标题翻译：非易失性存储器，制造方法及其工作方法
公开(公告)号：US20060289925A1
公开(公告)日：2006-12-28
申请号：US11306093
申请日：2005-12-15
申请人： Wei-Zhe Wong , Ching-Sung Yang
发明人： Wei-Zhe Wong , Ching-Sung Yang
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L29/7887 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L29/4232 , H01L29/42324 , H01L29/42328 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.
摘要翻译：提供至少包括衬底，存储单元和源极/漏极区域的非易失性存储器。存储单元设置在基板上，并且至少包括第一存储单元和第二存储单元。其中，第一存储单元从衬底向上包括浮动栅极和第一控制栅极。第二存储器单元设置在第一存储器单元的侧壁上，并且包括电荷捕获层和第二控制栅极。两个源极/漏极区域设置在存储单元两侧的衬底中。

68. 发明申请

US20060186481A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF 审中-公开
标题翻译：非易失性存储器及其制造方法及其工作方法
公开(公告)号：US20060186481A1
公开(公告)日：2006-08-24
申请号：US11161312
申请日：2005-07-29
申请人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
发明人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
IPC分类号： H01L29/76
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A non-volatile memory having many memory cell columns is provided. Each memory cell column includes a plurality of memory cells formed on a substrate. A deep p-type well is disposed in the substrate and an n-type well is disposed on the deep p-type well. A shallow p-type well isolated by device isolation structures is disposed on the n-type well. A select unit is disposed on one side of each memory cell column. An n-type source region is disposed in the substrate adjacent to the select unit. An n-type drain region is disposed in the substrate on the other side of the memory cell column. A bit line is disposed on the substrate. The bit line connects with the n-type drain region through a conductive plug. The conductive plug penetrates the junction between the n-type drain region and the shallow p-type well and forms a short between them.
摘要翻译：提供了具有许多存储单元列的非易失性存储器。每个存储单元列包括形成在基板上的多个存储单元。在衬底中设置深p型阱，在深p型阱上设置n型阱。通过器件隔离结构隔离的浅P型阱设置在n型阱上。选择单元设置在每个存储单元列的一侧。 n型源极区域设置在与选择单元相邻的衬底中。在存储单元列的另一侧的衬底中设置n型漏极区。位线设置在基板上。位线通过导电插头与n型漏极区域连接。导电插塞穿透n型漏极区和浅P型阱之间的结，并在它们之间形成短路。

69. 发明申请

US20060170038A1 NON-VOLATILE MEMORY AND MANUFACTURING AND OPERATING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造和操作方法
公开(公告)号：US20060170038A1
公开(公告)日：2006-08-03
申请号：US11161398
申请日：2005-08-02
申请人： Wei-Zhe Wong , Ching-Sung Yang
发明人： Wei-Zhe Wong , Ching-Sung Yang
IPC分类号： H01L29/94
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A plurality of select gate dielectric layers are disposed between the select gates and the substrate. A plurality of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A plurality of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers.
摘要翻译：提供非易失性存储器。提供具有多个沟槽和多个选择栅极的衬底。沟槽平行布置并沿第一方向延伸。每个选择栅极分别设置在两个相邻沟槽之间的衬底上。在选择栅极和衬底之间设置多个选择栅极电介质层。多个复合层设置在沟槽的表面上，并且每个复合层具有电荷捕获层。多个字线在第二方向上平行布置，其中每条字线填充相邻选择栅之间的沟槽并且设置在复合层之上。

70. 发明申请

US20060170026A1 NON-VOLATILE MEMORY AND FABRICATING METHOD AND OPERATING METHOD THEREOF 有权
标题翻译：非挥发性记忆及其制作方法及其操作方法
公开(公告)号：US20060170026A1
公开(公告)日：2006-08-03
申请号：US11162116
申请日：2005-08-29
申请人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
发明人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.
摘要翻译：提供非易失性存储器。衬底在其中具有至少两个隔离结构以限定有效区域。一个井位于基板中。浅掺杂区域位于井中。至少两个堆叠的栅极结构位于衬底上。袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。辅助栅极层位于堆叠栅极结构之间的衬底上。栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

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