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61. 发明授权

US06890819B2 Methods for forming PN junction, one-time programmable read-only memory and fabricating processes thereof 有权
标题翻译：用于形成PN结的方法，一次可编程只读存储器及其制造方法
公开(公告)号：US06890819B2
公开(公告)日：2005-05-10
申请号：US10605253
申请日：2003-09-18
申请人： Chao-I Wu , Ming-Hsiu Lee
发明人： Chao-I Wu , Ming-Hsiu Lee
IPC分类号： H01L21/336 , H01L27/10
CPC分类号： H01L27/10
摘要： A method for forming a PN junction is described. A stacked structure consisting of an N-doped (or P-doped) layer, a dielectric layer and a nucleation layer is formed, and then an insulating layer is formed having an opening therein. A P-doped (or N-doped) polysilicon or amorphous silicon layer is filled into the opening, and then annealed to convert into a single-crystal silicon layer. Then, the dielectric layer is broken down to form a PN junction.
摘要翻译：描述了形成PN结的方法。形成由N掺杂（或P掺杂）层，电介质层和成核层组成的堆叠结构，然后形成其中具有开口的绝缘层。将p掺杂（或N掺杂）多晶硅或非晶硅层填充到开口中，然后退火以转化为单晶硅层。然后，介电层被分解以形成PN结。

62. 发明授权

US6002114A Control device for an electric water heater 失效
标题翻译：电热水器控制装置
公开(公告)号：US6002114A
公开(公告)日：1999-12-14
申请号：US153044
申请日：1998-09-15
申请人： Ming-Hsiu Lee
发明人： Ming-Hsiu Lee
IPC分类号： F24H9/20 , G05D23/19 , H05B1/02
CPC分类号： G05D23/1931 , F24H9/2028
摘要： A control device installed in an electric water heater to control its operation, the control device including a water temperature control circuit and a power control circuit, the water temperature control circuit being formed of a water temperature detection circuit, which detects water temperature at the water inlet and the water outlet of the electric water heater, a water flow rate detection circuit, which detects the flow rate of water passing through the water inlet, a CPU, an indicator circuit controlled by the CPU to indicate the working conditions of the electric water heater, and a digital display controlled by the CPU to show the value of water temperature at the water outlet, the power control circuit being formed of a power supply circuit, a TRAIC triggering control circuit, which turns on the heating elements of the electric water heater alternatively subject AC phase change, a TRAIC power circuit, which provides the TRAIC triggering control circuit with the base power, an AC phase detection input circuit, a relay circuit controlled by the CPU to cut off power supply from the electric water heater when an abnormal condition occurs, a failure detection circuit, which outputs a signal to the CPU when an abnormal condition of the electric water heater is detected, causing the CPU to cut off power supply from the electric water heater, and an overheat protection circuit for overheat protection.
摘要翻译：一种安装在电热水器中以控制其操作的控制装置，所述控制装置包括水温控制电路和功率控制电路，所述水温控制电路由水温检测电路形成，所述水温检测电路检测所述水的水温电热水器的入口和出水口，检测通过入水口的水的流量的水流量检测电路，CPU，由CPU控制的指示电路，以指示电水的工作条件加热器和由CPU控制的数字显示器，以显示出水口的水温值，功率控制电路由电源电路，TRAIC触发控制电路构成，TRAIC触发控制电路接通电水的加热元件加热器交替相位变化，TRAIC电源电路，为TRAIC触发控制电路提供基本功率，a 交流相位检测输入电路，由CPU控制的继电器电路，当异常状态发生时切断电热水器的电源;故障检测电路，当电热水器的异常情况发生时，向CPU输出信号被检测到，导致CPU切断来自电热水器的电源，以及用于过热保护的过热保护电路。

63. 发明授权

US08891293B2 High-endurance phase change memory devices and methods for operating the same 有权
标题翻译：高耐久相变存储器件及其操作方法
公开(公告)号：US08891293B2
公开(公告)日：2014-11-18
申请号：US13472395
申请日：2012-05-15
申请人： Pei-Ying Du , Chao-I Wu , Ming-Hsiu Lee , Sangbum Kim , Chung Hon Lam
发明人： Pei-Ying Du , Chao-I Wu , Ming-Hsiu Lee , Sangbum Kim , Chung Hon Lam
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0004 , G11C13/0021
摘要： Phase change based memory devices and methods for operating such devices described herein overcome the set or reset failure mode and result in improved endurance, reliability and data storage performance. A high current repair operation is carried out in response to a set or reset failure of a phase change memory cell. The higher current repair operation can provide a sufficient amount of energy to reverse compositional changes in the phase change material which can occur after repeated set and reset operations. By reversing these compositional changes, the techniques described herein can recover a memory cell which experienced a set or reset failure, thereby extending the endurance of the memory cell. In doing so, phase change based memory devices and methods for operating such devices are provided which have high cycle endurance.
摘要翻译：基于相变的存储器件和用于操作这里描述的这种器件的方法克服了设置或复位故障模式并导致改进的耐久性，可靠性和数据存储性能。响应于相变存储单元的置位或复位故障执行高电流修复操作。更高的电流修复操作可以提供足够的能量来反转在重复设置和复位操作之后可能发生的相变材料的组成变化。通过颠倒这些组合变化，本文描述的技术可以恢复经历设置或复位故障的存储器单元，从而延长存储单元的耐久性。这样做，提供了具有高循环耐久性的基于相变的存储器件和用于操作这些器件的方法。

64. 发明授权

US08779408B2 Phase change memory cell structure 有权
标题翻译：相变存储单元结构
公开(公告)号：US08779408B2
公开(公告)日：2014-07-15
申请号：US13436203
申请日：2012-03-30
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： H01L47/00
CPC分类号： H01L45/1273 , G11C13/0004 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/126 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/148
摘要： A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
摘要翻译：本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

65. 发明申请

US20140036570A1 OPERATING METHOD FOR MEMORY DEVICE AND MEMORY ARRAY AND OPERATING METHOD FOR THE SAME 有权
标题翻译：用于存储器件和存储器阵列的操作方法及其操作方法
公开(公告)号：US20140036570A1
公开(公告)日：2014-02-06
申请号：US13567750
申请日：2012-08-06
申请人： Feng-Min Lee , Yu-Yu Lin , Ming-Hsiu Lee
发明人： Feng-Min Lee , Yu-Yu Lin , Ming-Hsiu Lee
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0033 , G11C13/004 , G11C2013/0047 , G11C2013/0052 , G11C2013/0073 , G11C2213/77
摘要： An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.
摘要翻译：提供了一种用于存储器件和存储器阵列的操作方法及其操作方法。存储器件的操作方法包括以下步骤。使存储器件处于置位状态。用于使存储器件处于设置状态的方法包括将第一偏置电压施加到存储器件。读取设置状态的存储器件。一种在设定状态下读取存储器件的方法，包括将第二偏置电压施加到存储器件。将恢复的偏置电压施加到存储器件。在施加第一偏置电压的步骤或施加第二偏置电压的步骤之后执行用于施加恢复偏压的步骤。

66. 发明申请

US20130242648A1 APPROACH FOR PHASE CHANGE MEMORY CELLS TARGETING DIFFERENT DEVICE SPECIFICATIONS 有权
标题翻译：相位改变记忆细胞的方法，针对不同的设备规格
公开(公告)号：US20130242648A1
公开(公告)日：2013-09-19
申请号：US13421718
申请日：2012-03-15
申请人： Matthew J. BrightSky , Roger W. Cheek , Ming-Hsiu Lee
发明人： Matthew J. BrightSky , Roger W. Cheek , Ming-Hsiu Lee
IPC分类号： G11C11/00 , H01L21/8239
CPC分类号： G11C13/0004 , G11C13/0033 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1641 , H01L45/1675
摘要： A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property.
摘要翻译：存储器芯片以及在单个晶片上制造具有不同编程性能和保持特性的存储器件的方法。一种方法包括在晶片上沉积相变材料的第一界限区域，并在晶片上沉积相变材料的第二有界区域。该方法包括改变相变材料的第一有界区域的开关体积的化学成分。该方法包括在相变材料的第一有界区域中形成具有相变材料的修改的开关体积的第一存储单元，以及相变材料的第二有界区域中的第二存储单元，具有未改变的相变材料的开关体积，例如第一存储单元具有第一保留特性，而第二存储单元具有第二保留特性。第一保留性与第二保留性不同。

67. 发明授权

US08437192B2 3D two bit-per-cell NAND flash memory 有权
标题翻译： 3D双比特单元NAND闪存
公开(公告)号：US08437192B2
公开(公告)日：2013-05-07
申请号：US12785291
申请日：2010-05-21
申请人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
发明人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
IPC分类号： G11C16/00 , G11C16/02 , G11C16/04 , G11C5/02 , G11C5/06
CPC分类号： H01L27/11578 , G11C16/0483 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.
摘要翻译： 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。包括导电材料层的共同源平面位于顶部和底部存储立方体之间。源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

68. 发明授权

US08374019B2 Phase change memory with fast write characteristics 有权
标题翻译：具有快速写入特性的相变存储器
公开(公告)号：US08374019B2
公开(公告)日：2013-02-12
申请号：US12985253
申请日：2011-01-05
申请人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
发明人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： H01L45/06 , G11C11/005 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C14/00 , G11C2013/0083 , G11C2013/0092 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.
摘要翻译：一种包括可编程电阻存储单元的存储器件，包括电预应力目标存储单元。预应力目标存储单元具有较低电压转变阈值，较短持续时间设定间隔和较长复位状态保持特性之一。设备上包括偏置电路，用于控制预应力操作，以及应用对预应力存储单元进行修改的读取，置位和复位操作。

69. 发明授权

US08241928B2 Test structure and method for detecting charge effects during semiconductor processing 有权
标题翻译：用于在半导体处理期间检测电荷效应的测试结构和方法
公开(公告)号：US08241928B2
公开(公告)日：2012-08-14
申请号：US12777858
申请日：2010-05-11
申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
摘要翻译：半导体工艺测试结构包括电极，电荷俘获层和扩散区域。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

70. 发明申请

US20120187362A1 Phase Change Memory Cell Structure 有权
标题翻译：相变存储单元结构
公开(公告)号：US20120187362A1
公开(公告)日：2012-07-26
申请号：US13436203
申请日：2012-03-30
申请人： Ming-Hsiu Lee , Chieh-Fang Chen
发明人： Ming-Hsiu Lee , Chieh-Fang Chen
IPC分类号： H01L45/00
CPC分类号： H01L45/1273 , G11C13/0004 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/126 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/148
摘要： A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
摘要翻译：本文所述的存储单元包括存储元件，其包括覆盖导电触点的可编程电阻存储器材料。绝缘体元件包括从导电触点延伸到存储元件中的管状部分，管形部分具有近端和远端以及限定内部的内表面，近端与导电触点相邻。底部电极接触导电接触并在内部从近端向远端向上延伸，底部电极具有在第一接触表面处与远端相邻的顶表面接触存储元件。顶部电极通过存储元件与管状部分的远端分离，并在第二接触表面处接触存储元件，第二接触表面的表面积大于第一接触表面的表面积。

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