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    • 66. 发明授权
    • Circuit and method for a multiplexed redundancy scheme in a memory device
    • 存储器件中多路冗余方案的电路和方法
    • US06269035B1
    • 2001-07-31
    • US09687206
    • 2000-10-13
    • Timothy B. CowlesVictor WongJames S. CullumJeffrey P. Wright
    • Timothy B. CowlesVictor WongJames S. CullumJeffrey P. Wright
    • G11C700
    • G11C29/808
    • A semiconductor memory device including a memory-cell array divided into a plurality of memory sub-arrays that are arranged into rows and columns of memory cells. Each of the sub-arrays has a limited number of redundant rows and columns to repair defective memory cells. The redundant memory of at least two memory sub-arrays is coupled to an I/O line through a respective isolation circuit. A control circuit coupled to the isolation circuits selectively couples the redundant memory of the sub-arrays to the I/O line. Coupling the redundant memory of multiple sub-arrays facilitates using the redundant memory of one sub-array to repair the defective memory cells in other sub-arrays also coupled to the I/O line, when the redundant memory primarily associated with the other sub-arrays has been depleted.
    • 一种半导体存储器件,包括被划分成存储器单元的行和列的多个存储器子阵列的存储单元阵列。 每个子阵列具有有限数量的冗余行和列来修复有缺陷的存储单元。 至少两个存储器子阵列的冗余存储器通过相应的隔离电路耦合到I / O线。 耦合到隔离电路的控制电路选择性地将子阵列的冗余存储器耦合到I / O线。 耦合多个子阵列的冗余存储器有助于使用一个子阵列的冗余存储器来修复也耦合到I / O线的其他子阵列中的有缺陷的存储器单元,当主要与其他子阵列相关联的冗余存储器时, 阵列已经耗尽。