专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07818511B2 Reducing number of rejected snoop requests by extending time to respond to snoop request 失效
标题翻译：通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
公开(公告)号：US07818511B2
公开(公告)日：2010-10-19
申请号：US11847941
申请日：2007-08-30
申请人： Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。缓存中的“停止/重新排序单元”从互连中接收窥探请求。窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。仲裁机制选择来自处理器的窥探请求或请求。如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。请求可能会稍后重新发送到选择器。该过程可以重复直到“n”个时钟周期。通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

62. 发明申请

US20100257316A1 Virtual Barrier Synchronization Cache Castout Election 失效
标题翻译：虚拟障碍同步缓存铸造选举
公开(公告)号：US20100257316A1
公开(公告)日：2010-10-07
申请号：US12419343
申请日：2009-04-07
申请人： Ravi K. Arimilli , Guy L. Guthrie , Michael Siegel , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , Michael Siegel , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F9/30101 , G06F9/3851 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units. The responsibility is transferred via an election held over the interconnect fabric.
摘要翻译：数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元，访问虚拟屏障同步区域。多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括高速缓存控制器和从系统存储器的虚拟屏障同步区域缓存VBSR行的高速缓存阵列。响应于来自其处理器核心的第一VBSR线路的存储器访问请求的第一处理单元的高速缓存控制器将负责向第一虚拟屏障同步区域写回同时保存在第一VBSR线路的高速缓存阵列中的第二VBSR线路，第二和第三处理单元。通过互连结构上的选举来转移责任。

63. 发明授权

US07484046B2 Reducing number of rejected snoop requests by extending time to respond to snoop request 失效
标题翻译：通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
公开(公告)号：US07484046B2
公开(公告)日：2009-01-27
申请号：US11950717
申请日：2007-12-05
申请人： Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Benjiman L. Goodman , Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。缓存中的“停止/重新排序单元”从互连中接收窥探请求。窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。仲裁机制选择来自处理器的窥探请求或请求。如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。请求可能会稍后重新发送到选择器。该过程可以重复直到“n”个时钟周期。通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

64. 发明授权

US07478201B2 Data processing system, cache system and method for passively scrubbing a domain indication 失效
标题翻译：数据处理系统，缓存系统和被动清理域指示的方法
公开(公告)号：US07478201B2
公开(公告)日：2009-01-13
申请号：US11136652
申请日：2005-05-24
申请人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Scrubbing logic in a local coherency domain issues a domain query request to at least one cache hierarchy in a remote coherency domain. The domain query request is a non-destructive probe of a coherency state associated with a target memory block by the at least one cache hierarchy. A coherency response to the domain query request is received. In response to the coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.
摘要翻译：本地一致性域中的擦除逻辑向远程一致性域中的至少一个缓存层次结构发出域查询请求。域查询请求是由至少一个高速缓存层次结构与目标存储器块相关联的一致性状态的非破坏性探测。接收到域查询请求的一致性响应。响应于指示目标存储器块未被缓存在远程一致性域中的相关性响应，本地一致性域中的域指示被更新以指示目标存储器块被缓存，如果完全只在本地一致性内域。

65. 发明授权

US07447845B2 Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求由具有不同功能的状态机服务
公开(公告)号：US07447845B2
公开(公告)日：2008-11-04
申请号：US11457333
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/1416
摘要： A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
摘要翻译：数据处理系统包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录，至少一个服务于远程处理器核的存储器访问请求的窥探机器，以及服务于本地处理器核心的存储器访问请求的多个状态机。多状态机包括第一状态机，其具有能够服务的本地处理器核心的第一组存储器访问请求;以及第二状态机，其具有本地处理器核心的不同的第二组存储器访问请求，它能够维修。

66. 发明申请

US20080016278A1 Data Processing System, Processor and Method of Data Processing in which Local Memory Access Requests are Serviced on a Fixed Schedule 失效
标题翻译：数据处理系统，处理器和数据处理方法，其中本地存储器访问请求在固定时间表上服务
公开(公告)号：US20080016278A1
公开(公告)日：2008-01-17
申请号：US11457322
申请日：2006-07-13
申请人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Leo J. Clark , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/1425 , G06F12/0817 , G06F12/0897
摘要： A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
摘要翻译：处理单元包括本地处理器核心和耦合到本地处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的内容目录。缓存存储器还包括服务于第一组存储器访问请求的一个或多个状态机，通过参考数据阵列和固定时间表上的目录来指导第二组存储器访问请求的服务的仲裁器，地址冲突逻辑其通过检测和发出第二组中的活动存储器访问请求与后续存储器访问请求之间的地址冲突以及耦合到地址冲突逻辑的调度逻辑来保护第二组中的存储器访问请求。调度逻辑将第一组中的存储器访问请求分派到一个或多个状态机用于服务，并且向仲裁器发出信号，以根据固定的时间表对第二组中的存储器访问请求进行直接服务。

67. 发明授权

US08656121B2 Facilitating data coherency using in-memory tag bits and tag test instructions 失效
标题翻译：使用内存中标记位和标签测试指令促进数据一致性
公开(公告)号：US08656121B2
公开(公告)日：2014-02-18
申请号：US13109254
申请日：2011-05-17
申请人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/30076 , G06F12/0815 , G06F12/0875 , G06F12/1027 , G06F12/1425 , G06F21/79 , G06F2212/452
摘要： Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.
摘要翻译：通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联来提供对原始数据的数据修改的细粒度检测。保护位指示存储在相关联的粒子中的原始数据是否受到数据一致性的保护。保护位通过专用指令进行设置和清除。响应于尝试访问从原始数据获得的翻译数据，检查与原始数据相关联的保护位，以确定保护位是否不能指示原始数据的一致性，如果是，则丢弃启动翻译的数据以便于维持原始数据和翻译数据之间的数据一致性。

68. 发明授权

US08645644B2 Facilitating data coherency using in-memory tag bits and tag test instructions 失效
标题翻译：使用内存中标记位和标签测试指令促进数据一致性
公开(公告)号：US08645644B2
公开(公告)日：2014-02-04
申请号：US13451682
申请日：2012-04-20
申请人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/30076 , G06F12/0815 , G06F12/0875 , G06F12/1027 , G06F12/1425 , G06F21/79 , G06F2212/452
摘要： A method is provided for fine-grained detection of data modification of original data by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.
摘要翻译：提供了一种通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联的方法来对原始数据的数据修改进行细粒度检测。保护位指示存储在相关联的粒子中的原始数据是否受到数据一致性的保护。保护位通过专用指令进行设置和清除。响应于尝试访问从原始数据获得的翻译数据，检查与原始数据相关联的保护位，以确定保护位是否不能指示原始数据的一致性，如果是，则丢弃启动翻译的数据以便于维持原始数据和翻译数据之间的数据一致性。

69. 发明授权

US08489819B2 Victim cache lateral castout targeting 失效
标题翻译：受害者缓存横向倾斜定位
公开(公告)号：US08489819B2
公开(公告)日：2013-07-16
申请号：US12340511
申请日：2008-12-19
申请人： Guy L. Guthrie , Michael S. Siegel , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Michael S. Siegel , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/126 , G06F12/0811 , G06F12/0862
摘要： A data processing system includes a plurality of processing units coupled by an interconnect fabric. In response to a data request, a victim cache line is selected for castout from a first lower level cache of a first processing unit, and a target lower level cache of one of the plurality of processing units is selected based upon architectural proximity of the target lower level cache to a home system memory to which the address of the victim cache line is assigned. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that the target lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：数据处理系统包括通过互连结构耦合的多个处理单元。响应于数据请求，从第一处理单元的第一较低级别高速缓存中选择牺牲缓存行来进行舍弃，并且基于目标的体系结构接近来选择多个处理单元之一的目标下级高速缓存低级缓存到分配了受害者缓存行的地址的归属系统存储器。所述第一处理单元在所述互连结构上发出侧向锁定（LCO）命令，所述侧向锁定（LCO）命令标识要从所述第一低级缓存中抛出的所述牺牲缓存线，并且指示所述目标低级缓存是预期目的地。响应于指示LCO命令的成功的一致性响应，从第一低级缓存中删除受害者高速缓存行并保存在第二较低级高速缓存中。

70. 发明授权

US08412888B2 Cache-based speculation of stores following synchronizing operations 失效
标题翻译：同步操作后，存储器中基于缓存的推测
公开(公告)号：US08412888B2
公开(公告)日：2013-04-02
申请号：US12985590
申请日：2011-01-06
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0837 , G06F12/0895
摘要： A store request in enqueued in a store queue of a cache memory of the data processing system. The store request identifies a target memory block by a target address and specifies store data. While the store request and a barrier request older than the store request are enqueued in the store queue, a read-claim machine of the cache memory is dispatched to acquire coherence ownership of target memory block of the store request. After coherence ownership of the target memory block is acquired and the barrier request has been retired from the store queue, a cache array of the cache memory is updated with the store data.
摘要翻译：在数据处理系统的高速缓冲存储器的存储队列中排队的存储请求。存储请求通过目标地址识别目标存储器块并指定存储数据。当存储请求和存储请求之前的屏障请求在存储队列中排队时，调度高速缓冲存储器的读取机器以获取存储请求的目标存储器块的一致性所有权。在获取目标存储器块的一致性所有权并且屏障请求已经从存储队列中退出之后，用存储数据更新高速缓冲存储器的高速缓存阵列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式