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    • 69. 发明申请
    • Method for Simultaneous Modular Exponentiations
    • 同时模块化指标的方法
    • US20080144811A1
    • 2008-06-19
    • US11610919
    • 2006-12-14
    • Vinodh GopalErdinc OzturkKaan YuskelGunnar GaubatzWajdi FeghaliGilbert M. Wolrich
    • Vinodh GopalErdinc OzturkKaan YuskelGunnar GaubatzWajdi FeghaliGilbert M. Wolrich
    • H04L9/30
    • G06F7/723H04L9/302
    • The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
    • 本公开提供了一种用于执行模幂运算的方法。 该方法可以包括基于第一素数(p)模数的加密消息(X)生成第一余数(xp),并且基于加密消息(X)生成第二余数(xq),第二素数(q) )。 该方法还可以包括:基于第一余数(xp)产生第三余数(v1),所述第一余数(xp)基于所述第一余数(xp)生成第一素数(p)的第一私钥数(d1)并同时生成第四余数 第二余数(xq)升至第二素数(q)的第二私钥号(d2)。 该方法还可以包括从第三余数(v1)中减去第四余数(v2)以产生结果(v1-v2)并将结果(v1-v2)乘以常数(c)以产生第二结果。 该方法可以另外包括通过将第二结果以第一素数(p)取模并将第六余数(h)乘以第二素数(q)产生第三结果来产生第六余数(h)。 该方法还可以包括添加第三结果和第四余数(v2)以产生最终结果(Y),并且至少部分地基于最终结果(Y)生成公钥。 当然,在不脱离本实施例的情况下,可以进行许多替代,变化和修改。
    • 70. 发明申请
    • BITSTREAM PROCESSING USING COALESCED BUFFERS AND DELAYED MATCHING AND ENHANCED MEMORY WRITES
    • 使用加密缓存和延迟匹配和增强存储器写入的BITSTREAM处理
    • US20140156790A1
    • 2014-06-05
    • US13994129
    • 2011-12-23
    • Vinodh GopalJim D. GuilfordGilbert M. WolrichWajdi K. FeghailDeniz KarakoyunluErdinc OzturkMartin DixonKahraman Akdemir
    • Vinodh GopalJim D. GuilfordGilbert M. WolrichWajdi K. FeghailDeniz KarakoyunluErdinc OzturkMartin DixonKahraman Akdemir
    • H04L29/06
    • H04L65/607H03M7/30H03M7/3086H04L65/608H04L69/04H04L69/22H04W28/06
    • Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.
    • 用于处理比特流和字节流的方法和装置。 根据一个方面,使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。 使用匹配器来执行搜索字符串匹配操作,使用缩短的最大字符串长度搜索条件,导致生成具有数据和文字数据的令牌流。 对顺序相邻的令牌执行距离匹配操作,以确定它们是否包含相同的距离数据。 如果这样做,令牌的len值通过使用合并缓冲区来添加。 在检测到距离不匹配时,计算匹配串的最终合并长度,并将其与先前匹配距离一起作为合并令牌输出。 还公开了一种用于将可变长度令牌写入比特流的方案,在该比特流中,令牌数据被输入到比特累加器中,并且以消除分支错误预测的方式将每个令牌进行处理,并将其写入存储器(或高速缓存以随后写入存储器) 检测位累加器是满或接近满的操作。