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61. 发明授权

US07827343B2 Method and apparatus for providing accelerator support in a bus protocol 有权
标题翻译：在总线协议中提供加速器支持的方法和装置
公开(公告)号：US07827343B2
公开(公告)日：2010-11-02
申请号：US11858228
申请日：2007-09-20
申请人： Bradly George Frey , Steven Mark Thurber , Andrew Henry Wottreng
发明人： Bradly George Frey , Steven Mark Thurber , Andrew Henry Wottreng
IPC分类号： G06F13/36 , G06F15/173
CPC分类号： G06F13/4054
摘要： The present invention provides a method and apparatus for processing a bus protocol packet in order to provide accelerator support. A component receives a bus protocol packet having a requester identifier. The component looks up an agent routing field. The component routes the bus protocol packet to an accelerator agent based on the agent routing field. It processes the bus protocol packet at the accelerator agent based on the agent routing field.
摘要翻译：本发明提供了一种用于处理总线协议分组以便提供加速器支持的方法和装置。组件接收具有请求者标识符的总线协议分组。组件查找代理路由字段。该组件基于代理路由字段将总线协议数据包路由到加速器代理。它基于代理路由字段处理加速器代理处的总线协议数据包。

62. 发明授权

US07636772B1 Method and apparatus for dynamic retention of system area network management information in non-volatile store 有权
标题翻译：在非易失性存储中动态保留系统区域网络管理信息的方法和装置
公开(公告)号：US07636772B1
公开(公告)日：2009-12-22
申请号：US09692365
申请日：2000-10-19
申请人： Orvalle Theodore Kirby , Gregory Michael Nordstrom , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
发明人： Orvalle Theodore Kirby , Gregory Michael Nordstrom , Gregory Francis Pfister , Renato John Recio , Steven Mark Thurber
IPC分类号： G06F15/16 , G06F9/00 , G06F13/00
CPC分类号： G06F13/4022
摘要： A method in a network computing system for managing configuration information for a set of components in a network computing system. The configuration information is stored for the set of components in the network computing system to form stored configuration information. In the depicted examples, the components may be nodes or devices within nodes. Current configuration is obtained in response to a power cycle. The current configuration information is compared with the stored configuration information to form a comparison. The stored configuration information is updated if a difference is present in the comparison. The stored configuration information is used to configure the components when a power cycle occurs.
摘要翻译：一种用于管理网络计算系统中的一组组件的配置信息的网络计算系统中的方法。为网络计算系统中的组件集合存储配置信息以形成存储的配置信息。在所描绘的示例中，组件可以是节点内的节点或设备。响应于电源循环获得当前配置。将当前配置信息与存储的配置信息进行比较以形成比较。如果比较中存在差异，则更新所存储的配置信息。存储的配置信息用于在发生电源周期时配置组件。

63. 发明授权

US07552269B2 Synchronizing a plurality of processors 有权
标题翻译：同步多个处理器
公开(公告)号：US07552269B2
公开(公告)日：2009-06-23
申请号：US11622299
申请日：2007-01-11
申请人： Steven Mark Thurber , Andrew Henry Wottreng
发明人： Steven Mark Thurber , Andrew Henry Wottreng
IPC分类号： G06F13/00
CPC分类号： G06F9/3879 , G06F9/3004 , G06F9/30087
摘要： In a first aspect, a first method of synchronizing a plurality of processors of a system is provided. The first method includes the steps of (1) modifying a peripheral component interconnect express (PCIe) protocol to include a completion status encode associated with a synchronization command that indicates whether a condition of the synchronization command is met; (2) providing a system including (a) a memory; (b) a first processor coupled to the memory; (c) a second processor; and (d) an interconnect coupling the second processor to the first processor and the memory; and (3) employing the modified PCIe protocol on the interconnect. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种使系统的多个处理器同步的第一种方法。第一种方法包括以下步骤：（1）修改外围组件互连快速（PCIe）协议以包括与指示是否满足同步命令的条件的同步命令相关联的完成状态编码; （2）提供包括（a）存储器的系统; （b）耦合到存储器的第一处理器; （c）第二处理器; 和（d）将所述第二处理器耦合到所述第一处理器和所述存储器的互连; 和（3）在互连上采用修改的PCIe协议。提供了许多其他方面。

64. 发明申请

US20090083471A1 METHOD AND APPARATUS FOR PROVIDING ACCELERATOR SUPPORT IN A BUS PROTOCOL 有权
标题翻译：用于在总线协议中提供加速器支持的方法和装置
公开(公告)号：US20090083471A1
公开(公告)日：2009-03-26
申请号：US11858228
申请日：2007-09-20
申请人： Bradly George Frey , Steven Mark Thurber , Andrew Henry Wottreng
发明人： Bradly George Frey , Steven Mark Thurber , Andrew Henry Wottreng
IPC分类号： G06F13/00
CPC分类号： G06F13/4054
摘要： The present invention provides a method and apparatus for processing a bus protocol packet in order to provide accelerator support. A component receives a bus protocol packet having a requester identifier. The component looks up an agent routing field. The component routes the bus protocol packet to an accelerator agent based on the agent routing field. It processes the bus protocol packet at the accelerator agent based on the agent routing field.
摘要翻译：本发明提供了一种用于处理总线协议分组以便提供加速器支持的方法和装置。组件接收具有请求者标识符的总线协议分组。组件查找代理路由字段。该组件基于代理路由字段将总线协议数据包路由到加速器代理。它基于代理路由字段处理加速器代理处的总线协议数据包。

65. 发明申请

US20080189577A1 Isolation of Input/Output Adapter Error Domains 有权
标题翻译：输入/输出适配器错误域的隔离
公开(公告)号：US20080189577A1
公开(公告)日：2008-08-07
申请号：US12105955
申请日：2008-04-18
申请人： Richard Louis Arndt , Patrick Allen Buckland , Gregory Michael Nordstrom , Steven Mark Thurber
发明人： Richard Louis Arndt , Patrick Allen Buckland , Gregory Michael Nordstrom , Steven Mark Thurber
IPC分类号： G06F11/07
CPC分类号： G06F11/2736
摘要： Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.
摘要翻译：用于在数据处理系统中隔离输入/输出适配器错误域的方法，装置和系统。在一个输入/输出适配器中发生的错误与数据处理系统的其他输入/输出适配器隔离，主机桥中的功能将输入/输出适配器连接到数据处理系统的系统总线，从而允许使用低成本，行业标准交换机和主桥外部的桥梁。

66. 发明申请

US20080172507A1 Methods and Apparatus for Synchronizing a Plurality of Processors 有权
标题翻译：用于同步多个处理器的方法和装置
公开(公告)号：US20080172507A1
公开(公告)日：2008-07-17
申请号：US11622299
申请日：2007-01-11
申请人： Steven Mark Thurber , Andrew Henry Wottreng
发明人： Steven Mark Thurber , Andrew Henry Wottreng
IPC分类号： G06F13/42
CPC分类号： G06F9/3879 , G06F9/3004 , G06F9/30087
摘要： In a first aspect, a first method of synchronizing a plurality of processors of a system is provided. The first method includes the steps of (1) modifying a peripheral component interconnect express (PCIe) protocol to include a completion status encode associated with a synchronization command that indicates whether a condition of the synchronization command is met; (2) providing a system including (a) a memory; (b) a first processor coupled to the memory; (c) a second processor; and (d) an interconnect coupling the second processor to the first processor and the memory; and (3) employing the modified PCIe protocol on the interconnect. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种使系统的多个处理器同步的第一种方法。第一种方法包括以下步骤：（1）修改外围组件互连快速（PCIe）协议以包括与指示是否满足同步命令的条件的同步命令相关联的完成状态编码; （2）提供包括（a）存储器的系统; （b）耦合到存储器的第一处理器; （c）第二处理器; 和（d）将所述第二处理器耦合到所述第一处理器和所述存储器的互连; 和（3）在互连上采用修改的PCIe协议。提供了许多其他方面。

67. 发明申请

US20080126617A1 Message Signaled Interrupt Management for a Computer Input/Output Fabric Incorporating Dynamic Binding 审中-公开
标题翻译：结合动态绑定的计算机输入/输出结构的消息信号中断管理
公开(公告)号：US20080126617A1
公开(公告)日：2008-05-29
申请号：US11467816
申请日：2006-08-28
申请人： Sean Thomas Brownlow , James Arthur Lindeman , Gregory Michael Nordstrom , John Ronald Oberly , John Thomas O'Quin , Steven Mark Thurber , Timothy Joseph Torzewski
发明人： Sean Thomas Brownlow , James Arthur Lindeman , Gregory Michael Nordstrom , John Ronald Oberly , John Thomas O'Quin , Steven Mark Thurber , Timothy Joseph Torzewski
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/5077
摘要： An apparatus, program product and method dynamically bind Message Signaled Interrupt (MSI) resources shared by a plurality of clients to an interrupt facility in an MSI-capable computer. In addition, management of such bindings may be implemented using a platform independent interrupt manager capable of managing multiple MSI bindings between MSI resources to an interrupt facility, and interfaced with an underlying hardware platform of a computer through platform-specific encapsulation program code.
摘要翻译：一种装置，程序产品和方法将由多个客户端共享的消息信号中断（MSI）资源动态地绑定到支持MSI的计算机中的中断设备。此外，可以使用平台独立的中断管理器来实现这种绑定的管理，该中断管理器能够将MSI资源之间的多个MSI绑定管理到中断设备，并且通过特定于平台的封装程序代码与计算机的底层硬件平台接口。

68. 发明授权

US07076570B2 Method and apparatus for managing service indicator lights in a logically partitioned computer system 失效
标题翻译：用于管理逻辑分区计算机系统中的服务指示灯的方法和装置
公开(公告)号：US07076570B2
公开(公告)日：2006-07-11
申请号：US10424641
申请日：2003-04-25
申请人： George Henry Ahrens , Curtis Shannon Eide , Steven Mark Thurber
发明人： George Henry Ahrens , Curtis Shannon Eide , Steven Mark Thurber
IPC分类号： G06F3/00
CPC分类号： G06F9/5077 , G06F11/324
摘要： A low-level function which enforces logical partitioning establishes a set of virtual indicator lights for certain physical components, the virtual indicator lights being only data in memory, a separate set of virtual indicator lights corresponding to each respective partition. Processes running in a partition can switch and sense the virtual indicator lights corresponding to the partition, but have no direct capability to either switch or to sense the virtual lights of any other partition. The low-level enforcement function alone can switch the state of the physical indicator light, which is generally the logical OR of the virtual indicator lights of the different partitions.
摘要翻译：执行逻辑分区的低级功能为某些物理组件建立一组虚拟指示灯，虚拟指示灯只是存储器中的数据，对应于每个相应分区的单独的一组虚拟指示灯。在分区中运行的进程可以切换和感测与分区对应的虚拟指示灯，但是没有直接的能力来切换或感测任何其他分区的虚拟指示灯。低级执行功能单独可以切换物理指示灯的状态，这通常是不同分区的虚拟指示灯的逻辑或。

69. 发明授权

US06990528B1 System area network of end-to-end context via reliable datagram domains 失效
标题翻译：通过可靠的数据报域，端到端上下文的系统区域网络
公开(公告)号：US06990528B1
公开(公告)日：2006-01-24
申请号：US09692354
申请日：2000-10-19
申请人： Danny Marvin Neal , Renato John Recio , Steven Mark Thurber
发明人： Danny Marvin Neal , Renato John Recio , Steven Mark Thurber
IPC分类号： G06F15/16
CPC分类号： G06F3/0659 , G06F3/0605 , G06F3/067
摘要： A method for associating reliable datagram queue pairs with an underlying end-to-end context of a channel adapter is provided. The method comprises storing a reliable datagram domain (RDD) within the context of a reliable datagram queue pair (RD QP). The same RDD is stored within an end-to-end context (EEC). A partitioning key (P—key) is also stored within the EEC. The RDD cannot be accessed by consumer processes. In the case of incoming messages, the P—keys of the incoming data packet and EEC are compared. If P—keys match, then the RDD's of the RD QP and EEC are compared. If the RDD's match, the packet is processed normally. In the case of outgoing messages, the RDD's of the RD QP and EEC are first compared, and if they match, the P—Key of the EEC is inserted into the transport header of the data packet.
摘要翻译：提供了一种用于将可靠数据报队列对与信道适配器的底层端到端上下文相关联的方法。该方法包括在可靠数据报队列对（RD QP）的上下文中存储可靠数据报域（RDD）。相同的RDD存储在端到端上下文（EEC）中。分区键（P _{- 键）也存储在EEC中。消费者进程无法访问RDD。在传入消息的情况下，比较输入数据包和EEC的P _{- 键。如果P _{- 键匹配，则比较RD QP和EEC的RDD。如果RDD匹配，则该分组被正常处理。在传出消息的情况下，首先比较RD QP和EEC的RDD，如果匹配，则将EEC的密钥插入到数据包的传输报头中。}}}

70. 发明授权

US06973510B2 DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge 有权
公开(公告)号：US06973510B2
公开(公告)日：2005-12-06
申请号：US10953920
申请日：2004-09-29
申请人： Richard Louis Arndt , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Louis Arndt , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F13/28 , G06F3/00 , G06F3/06
CPC分类号： G06F13/28
摘要： A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus. The terminal bridge can examine the grant signals from the arbiter to the IOAs, to determine which set of range registers is to be used.

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