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61. 发明专利

JPS63318838A ERROR CONTROL COMMUNICATION METHOD 失效
公开(公告)号：JPS63318838A
公开(公告)日：1988-12-27
申请号：JP15352587
申请日：1987-06-22
申请人： OKI ELECTRIC IND CO LTD
发明人： NOGUCHI OSAMU , SUZUKI TAKAO
IPC分类号： H04L1/14 , H04L1/12
摘要： PURPOSE:To shorten the communication time and to improve the reliability for transmission of information by sending continuously the transmission data and then sending the transmission to be re-transmission after the transmission is through with other transmission data. CONSTITUTION:In a step 101 both the transmission data 1 and an error detectable CRC code are transmitted to the reception side from the transmission side. At the reception side the errors are checked based on all received data. When an error is checked, the data 1 is corrected and sent back to the transmission side in a step 103 with addition of the received CRC code. This returned data 1 is checked at the transmission side together with the CRC code. When these data and code are decided normal, they are transmitted continuously in steps 102 and 104 together with transmission data 2 and 3. While the transmission data is re-transmission in a step 106 after no data to be transmitted exists any more when decided as abnormal.

62. 发明专利

JPS63287118A ECHO CANCELLER 失效
公开(公告)号：JPS63287118A
公开(公告)日：1988-11-24
申请号：JP12103087
申请日：1987-05-20
申请人： OKI ELECTRIC IND CO LTD
发明人： MIYAMOTO RYOICHI , ITO YOSHIO , NOGUCHI OSAMU , SHOJI YASUO
IPC分类号： H04B3/23
摘要： PURPOSE:To detect the state of 2-way talking state without error by taking notice of flat delay of impulse response of an echo path so as to discriminate the two-way talking state. CONSTITUTION:The low-order stage of an adaptive digital filter (ADF) comprising a tape coefficient correction arithmetic circuit 12 consisting of adders 14-16 and a unit delay element 18 and a multiplier 19 corresponds to a flat delay and a two-way talking detection circuit 11 monitors tap coefficients a0-aL of the low-order stage. In the steady-state where no transmission signal exists, the tap coefficients a0-aL are converged nearly to zero, but in case of the two-way talking state, the tap coefficient a0-aL are increased and the two-way talking detection circuit 11 discriminates it to be in the 2-way talking state when the sum of the tap coefficients a0-aL exceeds a threshold value. The information is sent to a tap coefficient correction arithmetic circuit 12, where the correction and revision of the tap coefficients aL+1-aM of the high-order stage are stopped to fix them so as to prevent the correction in error.

63. 发明专利

JPS62245656A LSI CIRCUIT FOR SIGNAL PROCESSING 失效
公开(公告)号：JPS62245656A
公开(公告)日：1987-10-26
申请号：JP8818786
申请日：1986-04-18
申请人： OKI ELECTRIC IND CO LTD
发明人： NOGUCHI OSAMU , SUZUKI YUKIO , KAMOI HIDEKI , ONO SUSUMU
IPC分类号： H01L21/822 , H01L27/04
摘要： PURPOSE:To reduce the number of terminals of the title large scale integrated circuit by a method wherein, pertaining to the transmission and the reception of controlling information, a terminal is bidirectionally used by operating a switching circuit. CONSTITUTION:A bidirectional terminal 31 to be commonly used for an input circuit 15 and an output circuit 17 is provided. Said terminal 31 is used as one of the external terminals of a signal LSI circuit, and a change-over circuit 33 is connected to the terminal 31. The circuit 33 functions as the input terminal of the control signal with which the flow of program in the LSI circuit is compulsively switched. on the other hand, the circuit 33 can be switched so that the terminal 31 functions as the output terminal of the specific bit information of an internal bus. Accordingly, said circuit 33 is connected to the terminals 15 and 17 in the prescribed relation of connection. Consequently, the functions of the terminals for input and output of controlling information can be accomplished by using a common terminal, and the number of terminals used for transmission and reception of controlling information can be reduced by half.

64. 发明专利

JPS60220439A MEMORY ADDRESS CONTROL SYSTEM 失效
公开(公告)号：JPS60220439A
公开(公告)日：1985-11-05
申请号：JP7497984
申请日：1984-04-16
申请人： OKI ELECTRIC IND CO LTD
发明人： MIZUTANI HIDEO , NOGUCHI OSAMU , ANDOU HIROMI , FUKAZAWA ATSUSHI
IPC分类号： G06F12/02
摘要： PURPOSE:To control easily and quickly a memory address by providing a function to output the continuous addresses following the address defined by an instruction and a function to output addresses with a fixed delay secured from the timing of an instruction in addition to a function which outputs an address defined in an instruction field as it is. CONSTITUTION:A write address through order 16 is set at ''H'' and a head address set order 15 and an address delay order 17 are set at ''L'' respectively. Under such a condition, a gate 10 is effective and the input address information 1 is turned directly into the output address information 5 through a gate 13. When both orders 16 and 17 are set at ''L'', a continuous address gate signal 20 is set at ''H'' by an NOR circuit 19. Then a replaced continuous address is outputted through an effective gate 11 and the gate 13. When the order 17 is set at ''H'', the address input 1 is delayed by a flip-flop 8 and turned into a delay address output via an effective gate 12 and the gate 13.

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