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61. 发明授权

US07042251B2 Multi-function differential logic gate 失效
标题翻译：多功能差分逻辑门
公开(公告)号：US07042251B2
公开(公告)日：2006-05-09
申请号：US10833398
申请日：2004-04-28
申请人： David Meltzer , Muralikumar A. Padaparambil , Tat C. Wu
发明人： David Meltzer , Muralikumar A. Padaparambil , Tat C. Wu
IPC分类号： H03K19/20 , H03K19/094 , H03K19/084 , G11C18/00
CPC分类号： H03K3/356043 , H03D13/00 , H03L7/085
摘要： A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.
摘要翻译：全差分相位和频率检测器利用多功能差分逻辑门来实现差分和门操作，并提供完全差分D触发器。多功能差分逻辑门有四个输入，可以分为两对真和补两个信号。通过选择性地将输入重新分配给不同的信号对，可以使差分逻辑门提供同时的与/或非逻辑运算或同时的OR / NOR逻辑运算之一。差分D-触发器按照主/从配置实现，并且响应于输入时钟信号，输入复位输入和输入数据信号的真实和补码形式，并且还提供输出的真实和补充形式信号。相位和频率检测器中的所有组件都以CML电路配置为例。

62. 发明申请

US20050154733A1 Real-time change detection for network systems 审中-公开
标题翻译：网络系统的实时变化检测
公开(公告)号：US20050154733A1
公开(公告)日：2005-07-14
申请号：US11004289
申请日：2004-12-03
申请人： David Meltzer , Will Weisser , Doug Gisby , Jon Larimer , Jim Albert
发明人： David Meltzer , Will Weisser , Doug Gisby , Jon Larimer , Jim Albert
IPC分类号： G06F20060101 , G06F7/00 , G06F21/00 , H04L29/06
CPC分类号： H04L63/1416 , G06F21/554
摘要： A system for conducting continuous, real-time vulnerability detection of computer networks. The system includes a user interface, a scan engine and a database for obtaining and storing information concerning a network in general and devices and services that may interact with the network. The system provides continuous scanning of the network, each scan being compared with a predetermined baseline network configuration to determine if a change to the network has occurred. If a change has occurred, the system issues an alert informing a network administrator of the where and how the network has changed so appropriate action may be taken by the network administrator.
摘要翻译：一种用于进行计算机网络连续实时漏洞检测的系统。该系统包括用户界面，扫描引擎和数据库，用于获取和存储有关网络的信息，以及可能与网络交互的设备和服务。系统提供对网络的连续扫描，每个扫描与预定的基线网络配置进行比较，以确定是否发生了对网络的改变。如果发生更改，系统会发出警报通知网络管理员网络的位置和方式如何更改，网络管理员可能采取相应的措施。

63. 发明申请

US20050128018A1 Temperature compensation circuit 有权
标题翻译：温度补偿电路
公开(公告)号：US20050128018A1
公开(公告)日：2005-06-16
申请号：US10733143
申请日：2003-12-11
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03L1/02 , H03L1/00
CPC分类号： H03L1/022 , Y10S331/03
摘要： A temperature compensation circuit has multiple configurable modules to produce a compensation signal whose temperature characteristic curve is the inverse of the frequency-to-temperature characteristic curve of a specified oscillator. A set of first modules that produce first sub-signals directly proportional to temperature and a set of second modules that produce second sub-signals inversely proportional to temperature have their outputs summed at a summation node. Each module may adjust the strength and shaped of its temperature characteristic sub-signal, and each module may optionally be assigned a temperature offset that impedes the output of its corresponding sub-signal until the assigned temperature offset is reached. Each of the first and second modules includes a signal generator and an optional temperature offset circuit, which may be incorporated into the operation of the signal generator. To produce a compensation signal to compensate a SAW resonator, a first module having a temperature offset and being directly proportional to temperature is summed with a second module having no temperature offset and being inversely proportional to temperature.
摘要翻译：温度补偿电路具有多个可配置的模块，以产生一个补偿信号，其温度特性曲线是指定振荡器的频率 - 温度特性曲线的倒数。产生与温度成比例的第一子信号的一组第一模块和产生与温度成反比的第二子信号的一组第二模块，其输出在求和节点相加。每个模块可以调整其温度特性子信号的强度和形状，并且每个模块可以可选地分配一个温度偏移，该温度偏移阻碍其对应子信号的输出，直到达到分配的温度偏移。第一和第二模块中的每一个包括信号发生器和可选的温度偏移电路，其可并入到信号发生器的操作中。为了产生补偿信号以补偿SAW谐振器，具有温度偏移并与温度成正比的第一模块与不具有温度偏移并与温度成反比的第二模块相加。

64. 发明申请

US20050128017A1 Temperature compensation for a variable frequency oscillator without reducing pull range 失效
标题翻译：可变频率振荡器的温度补偿，不减小拉范围
公开(公告)号：US20050128017A1
公开(公告)日：2005-06-16
申请号：US10733094
申请日：2003-12-11
申请人： David Meltzer
发明人： David Meltzer
IPC分类号： H03B5/32 , H03B5/04 , H03B5/08 , H03B5/12 , H03L1/02 , H03L7/00 , H03L1/00
CPC分类号： H03L1/022 , H03B5/04 , H03L1/023 , H03L7/00 , Y10S331/03
摘要： A variable frequency oscillator having multiple, independent frequency control inputs, each coupled to a respective tuning sub-circuit. The tuning sub-circuits are connected in parallel with each other and with a resonator module, which may be a quartz crystal, inductor, or other reactance component. Each tuning sub-circuit consists of two varactors with their respective cathodes coupled to each other and to their corresponding frequency control input. By having the tuning sub-circuits connected in parallel to the resonator, the overall frequency pull range of each frequency control input remains unaffected by the activation of any other frequency control input. Preferably, at least one frequency control input is a temperature compensation control input that can maintain the variable oscillator insensitive to temperature variations while the remaining frequency control inputs provide functional frequency control.
摘要翻译：具有多个独立频率控制输入的可变频率振荡器，每个都耦合到相应的调谐子电路。调谐子电路彼此并联并且具有可以是石英晶体，电感器或其它电抗分量的谐振器模块。每个调谐子电路由两个变容二极管组成，它们各自的阴极相互耦合并连接到它们对应的频率控制输入端。通过使调谐子电路与谐振器并联连接，每个频率控制输入的总频率拉动范围不受任何其它频率控制输入的激活的影响。优选地，至少一个频率控制输入是温度补偿控制输入，其可以保持可变振荡器对温度变化不敏感，而剩余频率控制输入提供功能频率控制。

65. 发明授权

US06269039B1 System and method for refreshing memory devices 失效
标题翻译：刷新存储设备的系统和方法
公开(公告)号：US06269039B1
公开(公告)日：2001-07-31
申请号：US09542596
申请日：2000-04-04
申请人： Clair John Glossner, III , Erdem Hokenek , David Meltzer , Mayan Moudgill
发明人： Clair John Glossner, III , Erdem Hokenek , David Meltzer , Mayan Moudgill
IPC分类号： G11C702
CPC分类号： G11C11/406
摘要： A volatile memory device, in accordance with the present invention, includes an array of memory cells with at least two dummy cells disposed within the memory array. A driver is included for writing a first state to one of the at least two dummy cells and for writing a second state to another one of the at least two dummy cells. A comparison circuit compares the first state and the second state to a threshold to determine if a refresh of the array of memory cells is needed.
摘要翻译：根据本发明的易失性存储器件包括具有设置在存储器阵列内的至少两个虚设单元的存储单元阵列。包括驱动器，用于将第一状态写入至少两个虚拟单元之一，并将第二状态写入至少两个虚拟单元中的另一个。比较电路将第一状态和第二状态与阈值进行比较，以确定是否需要刷新存储器单元阵列。

66. 发明授权

US6038659A Method for using read-only memory to generate controls for microprocessor 失效
标题翻译：使用只读存储器生成微处理器控制的方法
公开(公告)号：US6038659A
公开(公告)日：2000-03-14
申请号：US968120
申请日：1997-11-12
申请人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , David Meltzer , Joel Abraham Silberman
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/382 , G06F9/30145 , G06F9/30196
摘要： A circuit for generating control signals used in a microprocessor has a storage array, such as a read-only memory (ROM) array, which contains a plurality of predefined logic patterns. An entry of the ROM array is selected, such as by the use of an address decoder, to choose a specific pattern, and the specific pattern is then modified based on a dynamic signal to generate an output control signal. The microprocessor may further predecode a base instruction using operation and operand source bits to yield a predecoded instruction having an address field whose value corresponds to the specific pattern. The dynamic signal can be based on whether an operand should be forwarded from a microprocessor component, and the specific pattern is then equivalent to a value for control signals required to execute an instruction when assuming that the operand should not be forwarded. Special control states can also be implemented, such as stall, halt, or scan data, through the use of particular code points in the ROM.
摘要翻译：用于产生在微处理器中使用的控制信号的电路具有存储阵列，诸如只读存储器（ROM）阵列，其包含多个预定逻辑模式。选择ROM阵列的入口，例如通过使用地址解码器来选择特定模式，然后基于动态信号修改特定模式以产生输出控制信号。微处理器可以进一步使用操作和源位来对基本指令进行预解码，以产生具有对应于特定模式的地址字段的预解码指令。动态信号可以基于操作数是否应该从微处理器组件转发，并且特定模式然后等于假设不应该转发操作数时执行指令所需的控制信号的值。还可以通过使用ROM中的特定代码点来实现特殊控制状态，例如停止，停止或扫描数据。

67. 发明授权

US5953283A Multi-port SRAM with reduced access requirements 失效
标题翻译：多端口SRAM，具有降低的访问要求
公开(公告)号：US5953283A
公开(公告)日：1999-09-14
申请号：US127332
申请日：1998-07-31
申请人： David Meltzer , Joel Abraham Silberman
发明人： David Meltzer , Joel Abraham Silberman
IPC分类号： G11C13/00 , G11C8/16 , G11C8/00
CPC分类号： G11C8/16
摘要： An improved multi-port SRAM that requires fewer access means, bit lines and sense amplifiers for multiport access. The number of access means can be reduced to ceiling (log.sub.2 B), where B is the number of access ports. The number of bit line sense amplifiers needed to achieve multiport access can also be reduced by the same factor as the number of access devices per cell. An efficient means is provided to select a correct access device among the plurality of access devices within the array and to condition a correct multiplexer select signal to couple a correct bit as specified by the port read address to the port read output. The access device selection can be implemented by a tree representation of all possible bit line and multiplexer select combinations. The tree representation can be implemented in hardware or software. Examples are provided of both a circuit and a tree walking algorithm that gives priority by port order. Alternatively, logic to select the bit lines and controls could give priority in bit order. In either case, examples are provided for modifying the strict priority order to avoid conflicts and obtain a correct solution.
摘要翻译：一种改进的多端口SRAM，其需要较少的访问方式，位线和用于多端口访问的读出放大器。访问方式的数量可以减少到上限（log2B），其中B是接入端口的数量。实现多端口访问所需的位线读出放大器的数量也可以减少与每个单元的访问设备数量相同的因素。提供了一种有效的方法来选择阵列内的多个访问设备中的正确的访问设备，并且调整正确的多路复用器选择信号以将由端口读取地址指定的正确位耦合到端口读取输出。访问设备选择可以通过所有可能的位线和多路复用器选择组合的树形表示来实现。树表示可以在硬件或软件中实现。提供了通过端口顺序优先的电路和树行走算法的示例。或者，选择位线和控制的逻辑可以按位顺序给出优先级。在这两种情况下，都提供了修改严格优先顺序以避免冲突并获得正确解决方案的示例。

68. 发明授权

US5875470A Multi-port multiple-simultaneous-access DRAM chip 失效
标题翻译：多端口多同时访问DRAM芯片
公开(公告)号：US5875470A
公开(公告)日：1999-02-23
申请号：US841029
申请日：1997-04-29
申请人： Jeffrey Harris Dreibelbis , Wayne Frederick Ellis , Thomas James Heller, Jr. , Michael Ignatowski , Howard Leo Kalter , David Meltzer
发明人： Jeffrey Harris Dreibelbis , Wayne Frederick Ellis , Thomas James Heller, Jr. , Michael Ignatowski , Howard Leo Kalter , David Meltzer
IPC分类号： G11C7/10 , G11C7/18 , G11C8/12 , G11C11/4097 , H01L29/78
CPC分类号： G11C7/1075 , G11C11/4097 , G11C7/18 , G11C8/12
摘要： Provides within a semiconductor chip a plurality of internal DRAM arrays connected to each section data bus. A cross-point switch simultaneously connects the plural section data buses to a corresponding plurality of port registers that transfer data between a plurality of ports (I/O pins) on the chip and the section data buses in parallel in either data direction to effectively support a high multi-port data rate to/from the memory chip. For any section, the data may be transferred entirely in parallel between the associated port and a corresponding port register, or the data may be multiplexed between each port and its port register in plural sets of parallel bits. Each of the DRAM banks in the chip is addressed and accessed in parallel with the other DRAM banks through a bank address control in the chip which receives all address requests from four processors in a computer system. Each section data bus is comprised of a large number of data lines that transfer data bits in parallel to/from all of DRAM cells in an address-selected row in one of the DRAM banks at a time in each section. The four DRAM section buses in the chip may be transferring data at the same time in independent directions to/from the four chip ports.
摘要翻译：在半导体芯片内提供连接到每个区段数据总线的多个内部DRAM阵列。交叉点开关同时将多段数据总线连接到对应的多个端口寄存器，其在芯片上的多个端口（I / O引脚）和数据总线之间在任一数据方向上并行传输数据，以有效支持与存储器芯片之间的高端口数据速率。对于任何部分，数据可以在相关联的端口和对应的端口寄存器之间完全并行地传送，或者数据可以在多个并行比特组中的每个端口与其端口寄存器之间进行复用。芯片中的每个DRAM组通过芯片中的存储体地址控制与其他DRAM组并行地寻址和访问，该存储器地址控制从计算机系统中的四个处理器接收所有地址请求。每个部分数据总线包括大量的数据线，其在每个部分中一次一个DRAM存储体中的地址选择行中的/从所有DRAM单元并行传送数据位。芯片中的四个DRAM部分总线可以在独立的方向上同时向四个芯片端口传送数据。

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