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61. 发明申请

US20100032767A1 STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY 有权
标题翻译：通过在CMOS电路中通过WAFER放置的锁定稳定性的结构和方法
公开(公告)号：US20100032767A1
公开(公告)日：2010-02-11
申请号：US12186802
申请日：2008-08-06
申请人： Phillip F. Chapman , David S. Collins , Steven H. Voldman
发明人： Phillip F. Chapman , David S. Collins , Steven H. Voldman
IPC分类号： H01L21/762 , H01L27/092
CPC分类号： H01L27/0921 , H01L21/743 , H01L21/76224 , H01L21/76898 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L23/481 , H01L27/092 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.
摘要翻译：一种制造半导体结构的方法包括：在衬底的背面形成沟槽; 在沟槽的表面上沉积掺杂剂; 在与沟槽相对的衬底的顶侧中形成浅沟槽隔离（STI）结构; 在基材中形成深井; 将掺杂剂扩散到深阱和衬底中; 在衬底中形成N阱和P阱; 并用导电材料填充沟槽。

62. 发明申请

US20090179276A1 Resistor Ballasted Transistors 失效
标题翻译：电阻镇流晶体管
公开(公告)号：US20090179276A1
公开(公告)日：2009-07-16
申请号：US11971962
申请日：2008-01-10
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L27/08
CPC分类号： H01L29/0847 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/086 , H01L29/0878 , H01L29/1083 , H01L29/7816 , H01L29/7817 , H01L29/7835 , H01L29/8605
摘要： A semiconductor chip comprises low voltage complementary metal oxide semiconductor (CMOS) sectors and high voltage lateral double diffused metal oxide semiconductor (LDMOS) sectors and at least one transistor within at least one of the low voltage CMOS sectors. The transistor has a semiconducting channel region within a substrate. A gate conductor is above the top layer of substrate, and the gate conductor is positioned above the channel region. A source/drain region is included in the substrate on a first side of the gate conductor and a lateral source/drain region is included in the substrate on a second side of the gate conductor opposite the first side. The lateral source/drain region is positioned a greater distance from the gate conductor than the source/drain region is positioned from the gate conductor. The embodiments herein also include a source/drain ballast resistor in the substrate between the lateral source/drain region and the gate conductor.
摘要翻译：半导体芯片包括低电压互补金属氧化物半导体（CMOS）扇区和高电压横向双扩散金属氧化物半导体（LDMOS）扇区以及至少一个低电压CMOS扇区内的至少一个晶体管。晶体管在衬底内具有半导体沟道区。栅极导体位于衬底的顶层之上，并且栅极导体位于沟道区的上方。源极/漏极区域包括在栅极导体的第一侧上的衬底中，并且横向源极/漏极区域包括在栅极导体的与第一侧相对的第二侧上的衬底中。横向源极/漏极区域比源极/漏极区域从栅极导体定位成距栅极导体更远的距离。本文的实施例还包括位于横向源极/漏极区域和栅极导体之间的衬底中的源极/漏极镇流电阻器。

63. 发明授权

US07549135B2 Design methodology of guard ring design resistance optimization for latchup prevention 失效
标题翻译：防止闭环防护的防护环设计电阻优化设计方法
公开(公告)号：US07549135B2
公开(公告)日：2009-06-16
申请号：US11566922
申请日：2006-12-05
申请人： Phillip F. Chapman , David S. Collins , Steven H. Voldman
发明人： Phillip F. Chapman , David S. Collins , Steven H. Voldman
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A design methodology is disclosed for optimizing guard ring design by optimizing the guard ring to power supply path resistance value between physical and/or virtual injection sources in a CMOS circuit and the corresponding power supply. By comparing the calculated guard ring to power supply path resistance value to resistance criteria derived from specifications, elements that need further redesign are identified. Repeated redesign with several redesign options eventually lead to an optimized guard ring structure that provides area-efficient and sufficient latchup protection for the CMOS circuit.
摘要翻译：公开了一种通过优化保护环到CMOS电路中的物理和/或虚拟注入源之间的供电路径电阻值和相应的电源来优化保护环设计的设计方法。通过将计算出的保护环与电源路径电阻值进行比较，可以确定需要进一步重新设计的元件。通过多次重新设计的重新设计，最终会导致优化的保护环结构，为CMOS电路提供区域高效和足够的锁存保护。

64. 发明申请

US20090127628A1 PRODUCT AND METHOD FOR INTEGRATION OF DEEP TRENCH MESH AND STRUCTURES UNDER A BOND PAD 有权
标题翻译：产品和方法，用于整合深层沥青网和结构桩
公开(公告)号：US20090127628A1
公开(公告)日：2009-05-21
申请号：US12256089
申请日：2008-10-22
申请人： Ephrem G. GEBRESELASIE , William T. Motsiff , Wolfgang Sauter , Steven H. Voldman
发明人： Ephrem G. GEBRESELASIE , William T. Motsiff , Wolfgang Sauter , Steven H. Voldman
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L27/0207 , H01L21/76224 , H01L21/823481 , H01L21/8249 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A structure includes a substrate. A trench structure is arranged within the substrate. A film is placed under an interlevel dielectric pad and between portions of the trench structure.
摘要翻译：一种结构包括基底。沟槽结构布置在衬底内。将薄膜放置在层间介质垫之下和沟槽结构的部分之间。

65. 发明授权

US07521359B2 Interconnect structure encased with high and low k interlevel dielectrics 失效
标题翻译：互连结构用高和低k层间电介质封装
公开(公告)号：US07521359B2
公开(公告)日：2009-04-21
申请号：US12054681
申请日：2008-03-25
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L21/44 , H01L21/8234 , H01L21/20
CPC分类号： H01L23/53295 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k material placed adjacent to at least one surface of the interconnect and extending over the thermal diffusion distance of the interconnect. The high-k material improves the critical current density of the interconnect by increasing the heat capacity and thermal conductivity of the interconnect. The high-k material can be placed on the sides, top and/or bottom of the interconnect. In multiple wire interconnects, the high-k material is placed between the wires of the interconnect. A low-k material is placed beyond the high-k material to reduce the capacitance of the interconnect. The combination of low-k and high-k materials provides an interconnect structure with improved ESD robustness and low capacitance that is well suited for an ESD device. The interconnect to the receiver, which does not carry a high current, is surrounded by a low-k material for reduced capacitance and performance advantages.
摘要翻译：一种用于改善具有静电放电（ESD）装置的集成电路的静电放电鲁棒性的结构和通过互连连接到焊盘的接收器网络。焊盘和ESD器件之间的互连具有邻近互连件的至少一个表面放置并且在互连的热扩散距离上延伸的高k材料。高k材料通过增加互连的热容和热导率来提高互连的临界电流密度。高k材料可以放置在互连的侧面，顶部和/或底部。在多线互连中，高k材料放置在互连线之间。低k材料放置在高k材料之外以减小互连的电容。低k和高k材料的组合提供了一种互连结构，具有改善的ESD稳健性和低电容，非常适合ESD器件。不具有高电流的接收器的互连被低k材料包围以减小电容和性能优点。

66. 发明授权

US07442996B2 Structure and method for enhanced triple well latchup robustness 有权
标题翻译：增强三井闭锁鲁棒性的结构和方法
公开(公告)号：US07442996B2
公开(公告)日：2008-10-28
申请号：US11275644
申请日：2006-01-20
申请人： David S. Collins , James A. Slinkman , Steven H. Voldman
发明人： David S. Collins , James A. Slinkman , Steven H. Voldman
IPC分类号： H01L29/76
CPC分类号： H01L27/0928 , H01L21/761 , H01L27/0921 , H01L29/1087
摘要： Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.
摘要翻译：公开了一种三阱CMOS器件结构，其通过在p阱下面添加n +掩埋层来解决闭锁的问题，以将p阱与p-衬底隔离，但也在n阱下方。该结构通过将n +掩埋层延伸到整个器件的下方来消除n阱和n +掩埋层之间的间隔问题。该结构还通过在n +掩埋层下方的整个器件下方或仅在器件的p阱侧下面的p +掩埋层提供阈值电压散射的问题，仅在n +掩埋层之下或之上）锁存稳健性可以进一步通过将在n +掩埋层和n阱之间消除侧向pnp，npn或pnpn器件和/或子集电极区域的隔离结构结合到器件中来改进。

67. 发明申请

US20080158747A1 RADIATION TOLERANT ELECTROSTATIC DISCHARGE PROTECTION NETWORKS 审中-公开
标题翻译：耐辐射静电放电保护网络
公开(公告)号：US20080158747A1
公开(公告)日：2008-07-03
申请号：US11837633
申请日：2007-08-13
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： G06F17/50 , H02H9/00
CPC分类号： H01L27/0259 , H01L2924/0002 , H03K19/0033 , H03K19/00338 , H01L2924/00
摘要： An ESD network. The ESD network including a redundant voltage clamping element in series with a first voltage clamping element between two voltage pads. The ESD network may be connected to a power voltage pad or a signal voltage pad either directly or through a dummy voltage pad. The voltage clamping elements may further comprise an array of unit cells wherein the array is electrically equivalent to single large transistors currently used in ESD networks. By creating an ESD network as an array of unit cells, benefits greater than those obtained by using a single transistor as a clamping or a trigger element are realized such as increased ballast resistance and less overall damage to the circuitry resulting from cosmic rays and particles.
摘要翻译：一个ESD网络。 ESD网络包括与两个电压焊盘之间的第一电压钳位元件串联的冗余电压钳位元件。 ESD网络可以直接或通过虚拟电压焊盘连接到电源电压焊盘或信号电压焊盘。电压钳位元件还可以包括单元电池阵列，其中阵列电气上等同于目前在ESD网络中使用的单个大型晶体管。通过将ESD网络创建为单元单元阵列，实现比通过使用单个晶体管作为钳位或触发元件获得的优点更大的益处，例如增加的镇流电阻和对由宇宙射线和粒子产生的电路的总体损坏。

68. 发明授权

US07334320B2 Method of making an electronic fuse with improved ESD tolerance 有权
标题翻译：制造具有改善的ESD耐受性的电子保险丝的方法
公开(公告)号：US07334320B2
公开(公告)日：2008-02-26
申请号：US11004846
申请日：2004-12-07
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01H69/02
CPC分类号： H01L23/5256 , H01L27/0248 , H01L2924/0002 , Y10T29/49107 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155 , H01L2924/00
摘要： Tolerance to ESD is increased in an electronic fuse by providing at least one non-conductive region adjacent to a conductive region on the surface of an insulator. Such an arrangement reduces the thermal stresses imposed on the insulator in high current applications. Where multiple conductive and adjacent non-conductive regions are disposed on an insulator, the fuse can fail in discrete steps, thus providing a well defined and easily detected transisition to a blown state, as well as providing a stepwise increase in resistance between prescribed resistance values.
摘要翻译：通过在绝缘体的表面上提供与导电区域相邻的至少一个非导电区域，在电子熔断器中增加对ESD的耐受性。这种布置降低了在大电流应用中施加在绝缘体上的热应力。在多个导电和相邻的非导电区域设置在绝缘体上的情况下，保险丝可以在离散的步骤中失效，从而提供良好限定且易于检测到的吹扫状态的接收，以及提供规定电阻值之间的电阻的逐步增加。

69. 发明申请

US20080023767A1 HIGH VOLTAGE ELECTROSTATIC DISCHARGE PROTECTION DEVICES AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS 审中-公开
标题翻译：高压静电放电保护装置和静电放电保护电路
公开(公告)号：US20080023767A1
公开(公告)日：2008-01-31
申请号：US11460286
申请日：2006-07-27
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L23/62
CPC分类号： H01L29/7391 , H01L27/0255 , H01L27/0629 , H01L29/0649 , H01L29/0653 , H01L29/0834 , H01L29/0878 , H01L29/1045 , H01L29/7816 , H01L29/7835 , H01L29/8611 , H01L29/866
摘要： High-voltage ESD devices and circuits using the high-voltage ESD devices. The high-voltage ESD devices include an N-tub in a P-type substrate; a graded anode having a first P-type region in a second P-type region and located within the N-tub, a concentration of P-type dopant in the first P-type region being greater than a concentration of P-type dopant in the second P-type region; and a graded cathode having a first N-type region in a second N-type region and located within the N-tub, a concentration of N-type dopant in the first N-type region being greater than a concentration of N-type dopant in the second N-type region.
摘要翻译：使用高压ESD器件的高压ESD器件和电路。高压ESD器件包括P型衬底中的N形槽; 在第二P型区域中具有第一P型区域并位于N型桶内的渐变阳极，第一P型区域中的P型掺杂剂的浓度大于P型掺杂剂的浓度第二个P型区域; 以及在第二N型区域中具有第一N型区域并位于N型槽内的渐变阴极，第一N型区域中的N型掺杂剂的浓度大于N型掺杂剂的浓度在第二个N型区域。

70. 发明授权

US07282771B2 Structure and method for latchup suppression 失效
标题翻译：闭锁抑制的结构和方法
公开(公告)号：US07282771B2
公开(公告)日：2007-10-16
申请号：US10905878
申请日：2005-01-25
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L29/76
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0921 , H01L27/0928
摘要： A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped region is placed under semiconductor devices of the first polarity and under the well region contact region. Additionally, the structure may further include a deep trench (DT) structure and trench isolation (TI) structure to further improve latchup robustness.
摘要翻译：一种用于集成电路的方法和结构，该集成电路包括第一极性的衬底，第二极性的合并三阱区域和第二极性的掺杂区域邻接阱区域。掺杂区域适于抑制集成电路中的闩锁。将掺杂区域放置在第一极性的半导体器件之下并且位于阱区域接触区域下方。另外，该结构还可以包括深沟槽（DT）结构和沟槽隔离（TI）结构，以进一步提高闭锁鲁棒性。

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