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61. 发明申请

US20090141733A1 ALGORTIHM AND SYSTEM FOR SELECTING ACKNOWLEDGMENTS FROM AN ARRAY OF COLLAPSED VOQ'S 失效
标题翻译：从收集的VOQ的阵列中选择确认的算法和系统
公开(公告)号：US20090141733A1
公开(公告)日：2009-06-04
申请号：US12365091
申请日：2009-02-03
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/56
CPC分类号： H04L49/3027 , H04L49/103 , H04L49/201 , H04L49/3045
摘要： A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time. Analyzing all the ingress ports holding at least one data packet, from the lesser degree of freedom to the greater degree of freedom, the algorithm determines as many virtual output queues as possible, in the limit of the number of ingress ports (an ingress port may send only one packet per packet-cycle).
摘要翻译：一种用于使用请求/确认机制来选择在折叠虚拟输出排队阵列（cVOQ）切换核心中切换的分组的方法。根据该方法，选择一组有效的虚拟输出队列（每个入口适配器最多有一个虚拟输出队列），同时保持算法足够简单，以允许其在快速状态机中实现。为了确定每个被授权发送分组的一组虚拟输出队列，该算法基于入射和出口适配器状态的自由度。例如，从折叠的虚拟输出排队阵列导出的自由度可以表示入口端口可以发送分组的出口端口的数量，或出口端口可以从其接收分组的入口端口的数量，给定时间分析至少一个数据包的入口端口，从较小的自由度到较大的自由度，该算法在入口端口数量的限制中尽可能地确定尽可能多的虚拟输出队列（入口端口可能每个分组周期只发送一个分组）。

62. 发明授权

US07477685B2 Method and systems for analyzing the quality of high-speed signals 失效
标题翻译：分析高速信号质量的方法和系统
公开(公告)号：US07477685B2
公开(公告)日：2009-01-13
申请号：US11774572
申请日：2007-07-07
申请人： Alain Blanc , Patrick Jeanniot
发明人： Alain Blanc , Patrick Jeanniot
IPC分类号： H04B3/46 , H04Q1/20
CPC分类号： H04L1/20
摘要： Methods and systems for analyzing the quality of high-speed signals are provided, wherein a high speed signal is sampled simultaneously a plurality of times during a sampling clock period at each of a plurality of phase rotator positions to generate a plurality of partial values, wherein subset pluralities of the partial values are associated to phase rotator positions. The partial values are combined into a global value which is analyzed to determine a quality of the high speed signal. Phase rotator behavior may also be analyzed to determine signal quality. A best position to lock a phase rotator when determining signal quality may be determined from a graphic characterization of a phase rotator position distribution.
摘要翻译：提供了用于分析高速信号质量的方法和系统，其中在多个相位旋转器位置中的每个相位旋转器位置处的采样时钟周期期间，高速信号被同时多次采样以产生多个部分值，其中子集多个部分值与相位旋转器位置相关联。将部分值组合成全局值，该值被分析以确定高速信号的质量。也可以分析相位旋转器行为以确定信号质量。确定信号质量时锁定相位旋转器的最佳位置可以从相位旋转器位置分布的图形表征来确定。

63. 发明申请

US20080267206A1 CAM BASED SYSTEM AND METHOD FOR RE-SEQUENCING DATA PACKETS 有权
标题翻译：基于CAM的系统和用于重新排序数据包的方法
公开(公告)号：US20080267206A1
公开(公告)日：2008-10-30
申请号：US12123602
申请日：2008-05-20
申请人： Alain Blanc , Rene Glaise , Michel Poret , Rene Gallezot
发明人： Alain Blanc , Rene Glaise , Michel Poret , Rene Gallezot
IPC分类号： H04L12/56
CPC分类号： H04L67/1002 , H04L47/50 , H04L49/1523 , H04L49/3045 , H04L49/552 , H04L49/9094
摘要： An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.
摘要翻译：该系统的一个实施例在具有至少一个出口适配器的并行分组交换机体系结构中操作，所述出口适配器布置成接收从多个入口适配器发出的数据分组，并且通过多个独立交换平面切换。每个接收到的数据分组属于多个序列中的一个数据分组序列，其中数据分组根据数据分组的至少优先级分配的分组序列号（PSN）进行编号。由至少一个出口适配器接收的每个数据分组具有源标识符，用于标识从其发出的入口适配器。用于恢复接收到的数据分组的序列的系统在出口适配器内操作，并且包括用于在分配的分组缓冲器位置临时存储每个接收的数据分组的缓冲器，控制器和耦合到存储装置和提取装置的确定装置。

64. 发明授权

US07400629B2 CAM based system and method for re-sequencing data packets 有权
标题翻译：基于CAM的系统和重新排序数据包的方法
公开(公告)号：US07400629B2
公开(公告)日：2008-07-15
申请号：US10723834
申请日：2003-11-26
申请人： Alain Blanc , Rene Glaise , Michel Poret , Rene Gallezot
发明人： Alain Blanc , Rene Glaise , Michel Poret , Rene Gallezot
IPC分类号： H04L12/28
CPC分类号： H04L67/1002 , H04L47/50 , H04L49/1523 , H04L49/3045 , H04L49/552 , H04L49/9094
摘要： A system for resequencing data packets is disclosed. In a preferred embodiment, the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter is further having a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location. Furthermore, controller to extract the packet sequence number, the source identifier and the priority level of each stored data packet. And determination means coupled to the storing means and to the extracting means allow to determine for each sequence of data packet the order of the data packets to be output from the egress adapter.
摘要翻译：公开了一种用于重新排序数据包的系统。在优选实施例中，系统以并行分组交换架构操作，其具有布置成接收从多个入口适配器发出并通过多个独立交换平面切换的数据分组的至少一个出口适配器。每个接收到的数据分组属于多个序列中的一个数据分组序列，其中数据分组根据数据分组的至少优先级分配的分组序列号（PSN）进行编号。由至少一个出口适配器接收的每个数据分组还具有源标识符以识别从其发出的入口适配器。用于恢复接收到的数据分组的序列的系统在出口适配器内操作，并且包括用于在分配的分组缓冲器位置临时存储每个接收到的数据分组的缓冲器。此外，控制器提取每个存储的数据包的包序列号，源标识符和优先级。以及耦合到所述存储装置并且所述提取装置的确定装置允许针对每个数据分组序列确定要从所述出口适配器输出的数据分组的顺序。

65. 发明授权

US07382792B2 Queue scheduling mechanism in a data packet transmission system 失效
标题翻译：数据包传输系统中的队列调度机制
公开(公告)号：US07382792B2
公开(公告)日：2008-06-03
申请号：US10065808
申请日：2002-11-21
申请人： Alain Blanc , Bernard Brezzo , Rene Gallezot , Francois Le Mauf , Daniel Wind
发明人： Alain Blanc , Bernard Brezzo , Rene Gallezot , Francois Le Mauf , Daniel Wind
IPC分类号： H04L12/28
CPC分类号： H04L47/6215 , H04L47/2458 , H04L47/28 , H04L47/50 , H04L47/527 , H04L47/6285 , H04W28/14 , H04W72/1242
摘要： A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank, and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides at each packet cycle a value N defining the priority rank to be considered by the queue scheduler whereby a data packet is read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm.
摘要翻译：在数据分组传输系统中的队列调度机制，包括用于发送数据分组的传输设备的数据分组传输系统，用于接收数据分组的接收设备，分别与一组优先级相关联的一组队列设备，每个优先级由用于将由传输设备发送的每个数据分组存储到与其优先级相对应的队列设备中的优先等级，以及队列调度器，用于在每个分组周期读取由普通优先级抢占算法确定的队列中的一个队列中的分组。队列调度机制包括在每个分组周期提供定义要由队列调度器考虑的优先级的值N的信用设备，由队列调度器从对应于优先级N的队列设备读取数据分组，而不是队列设备由普通优先级抢占算法确定。

66. 发明申请

US20050063301A1 METHOD AND SYSTEM TO ENABLE AN ADAPTIVE LOAD BALANCING IN A PARALLEL PACKET SWITCH 失效
标题翻译：在平行分组开关中启用自适应负载平衡的方法和系统
公开(公告)号：US20050063301A1
公开(公告)日：2005-03-24
申请号：US10711320
申请日：2004-09-10
申请人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
发明人： Rene Glaise , Alain Blanc , Francois Le Maut , Michel Poret
IPC分类号： H04J3/14 , H04L12/54 , H04L12/56
CPC分类号： H04L47/125 , H04L49/1523 , H04L49/25 , H04L49/30 , H04L49/3045
摘要： A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g., for replacing the defective individual switching plane or device.
摘要翻译：基于在入口端口适配器和折叠虚拟输出队列（cVOQ）阵列之间交换的请求和确认的监视来适应并行分组交换机（PPS）的平面上的入局业务的负载平衡的方法和系统，位于平面开关芯内。根据本发明，至少一个计数器在每个入口端口适配器中被关联到要监视的每个单独的切换平面或设备。当将请求发送到相应的单独的交换平面或设备时，这些计数器中的每一个递增，并且当从该单独的交换平面或设备接收到确认时递减。当相同入口端口适配器的计数器所取值的范围达到预定阈值时，较少（或无））进入流量进一步传输到与较高值计数器相关联的单独交换平面或设备。也可能引起报警信号，例如用于更换有缺陷的单独开关平面或装置。

67. 发明申请

US20050053077A1 System and method for collapsing VOQ'S of a packet switch fabric 有权
标题翻译：用于折叠分组交换结构的VOQ的系统和方法
公开(公告)号：US20050053077A1
公开(公告)日：2005-03-10
申请号：US10894582
申请日：2004-07-20
申请人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
发明人： Alain Blanc , Rene Glaise , Francois Le Maut , Michel Poret
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L47/10 , H04L47/263 , H04L47/30 , H04L49/103 , H04L49/3027 , H04L49/3045
摘要： A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.
摘要翻译：公开了一种在共享存储器交换机核心中避免分组业务拥塞的系统和方法，同时显着地减少了交换机核心和相关联的出口缓冲器中的共享存储器的数量。根据本发明，分组交换结构的所有入口适配器的虚拟输出排队（VOQ）被折叠到其中央交换机核心中以允许有效的流控制。数据包从入口缓冲区传输到交换机核心受到请求/确认的机制。因此，只有当交换机核心才能将其转发到相应的出口缓冲区时，才将数据包从虚拟输出队列传输到共享存储交换机内核。基于令牌的机制允许交换机核心确定出口缓冲区的占用水平。因此，由于交换机核心知道输入和输出适配器的状态，因此能够优化分组交换并避免分组拥塞。此外，由于分组只有在可以发送到对应的出口缓冲器的情况下才允许在交换机核心中，所以共享存储器被减少。

68. 发明授权

US06667955B1 Switching fabric system having at least one subsystem including switch core elements arranged in port expansion architecture 失效
标题翻译：具有至少一个子系统的交换结构系统包括以端口扩展架构布置的交换机核心元件
公开(公告)号：US06667955B1
公开(公告)日：2003-12-23
申请号：US09315907
申请日：1999-05-20
申请人： Alain Blanc , Sylvie Gohl , Alain Pinzaglia , Menahem Kaplan
发明人： Alain Blanc , Sylvie Gohl , Alain Pinzaglia , Menahem Kaplan
IPC分类号： H04J116
CPC分类号： H04Q3/52 , H04L12/5601 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/455 , H04L2012/5609 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13167 , H04Q2213/13353
摘要： A Switch Fabric system comprising at least one Switch Fabric subsystem (100, 200) further including a set of Switch cores elements (111, 112, 121, 122) that are mounted in a port expansion permitting attachment of at least a first and second sets of Protocol Adapters (1, 2) under a routing control process. A Primary Switch controller (PSC) has a complete knowledge of the topology of the switch, e.g., the number of subsystems, the nature of the port expansion etc., while each Secondary Switch Controller only has a limited knowledge of that topology. One particular Switch Core (111, 211) which has a full-duplex communication capability in each Subsystem is assigned the key function to interface communication between the PSC and the other SSC in a same Switch Fabric Subsystem.
摘要翻译：一种交换矩阵系统，包括至少一个交换结构子系统（100,200），其还包括一组交换机核心元件（111,112,121,122），其安装在端口扩展中，允许至少连接第一和第二组的协议适配器（1,2）。主交换机控制器（PSC）完全了解交换机的拓扑结构，例如子系统的数量，端口扩展的性质等等，而每个辅助交换机控制器只对该拓扑结构的知识有限。在每个子系统中具有全双工通信能力的特定交换机核心（111,211）被分配为在相同交换结构子系统中的PSC和其他SSC之间的通信的关键功能。

69. 发明授权

US06661786B1 Service message system for a switching architecture 失效
公开(公告)号：US06661786B1
公开(公告)日：2003-12-09
申请号：US09315446
申请日：1999-05-20
申请人： Jean-Claude Abbiate , Alain Blanc , Bernard Brezzo , Sylvie Gohl , Michel Poret
发明人： Jean-Claude Abbiate , Alain Blanc , Bernard Brezzo , Sylvie Gohl , Michel Poret
IPC分类号： H04L1250
CPC分类号： H04L49/1523 , H04L49/552
摘要： A service message system for a switching architecture including at least one Switch Fabric (10, 20) comprising a switch core (15, 25) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the different Port adapters (30, 31). Each SCAL elements particularly includes a SCAL receive element (11-i) and a SCAL Xmit element (12-i) for the respective access to one input port and one output port via serial links. The service message is based on the use of a Cell qualifier field at the beginning of each cell, which comprises a first and a second field. The first field is the Filtering Control field which permits an easy decoding of a service message cell, when applicable. The second field is used for determining which particular type of service message is conveyed via the cell. Following the Cell qualifier is the Switch Routing Header (SRH) which permits the characterization of the destination of the cell and is used for controlling the routing process. Preferably, the service message is used in a fault tolerance configuration where two different Switch Fabrics act as a standby to each other and shares a part of the traffic. Each one is configured as a default routing path for some ports adapters and a backup path for the others. In that particular configuration, the service message system of the invention uses the first field of the Cell qualifier to transport a Direct filtering command causing the Switch fabric to route the cell when the SRH is representative of its default output port destination. Conversely, the first field may transport a Reverse filtering command in the first field that causes the Switch fabric to reverse the default routing process. The first field is also used for characterizing a service message cell which the second field indicates the accurate type. Particularly, two types are used for the production of the filling cells when no data cell is to be transmitted at a particular location of the switching architecture.

70. 发明授权

US06570845B1 Switching system including a mask mechanism for altering the internal routing process 失效
标题翻译：切换系统包括用于改变内部路由过程的掩码机制
公开(公告)号：US06570845B1
公开(公告)日：2003-05-27
申请号：US09317322
申请日：1999-05-24
申请人： Alain Blanc , Bernard Brezzo , Alain Saurel
发明人： Alain Blanc , Bernard Brezzo , Alain Saurel
IPC分类号： G06F1100
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/153 , H04L49/256 , H04L49/309 , H04L2012/5627 , H04L2012/5681
摘要： A switching system receives a data cell from a set of n input ports for routing to one or more output ports in accordance with the contents of a bitmap value retrieved from the cell upon its receipt. The system has a module comprising a shared buffer for storing the cells which are to be routed and a mask mechanism with a mask register for altering the value of the bitmap before it is used for controlling the routing process. As a result of operation of the mask mechanism, a cell is either transported to an output port or discarded. Two switching systems are combined in first and second switch fabrics, each having a switch core and a set of switch core access layer (SCAL) elements. Each SCAL element respectively comprises a SCAL Receive element and a SCAL Xmit element for permitting access to input and output ports of one of the switching systems.
摘要翻译：交换系统根据从单元接收到的位图值的内容，从一组n个输入端口接收用于路由到一个或多个输出端口的数据单元。该系统具有模块，该模块包括用于存储待路由的单元的共享缓冲器和具有用于在用于控制路由过程之前改变位图的值的掩码寄存器的掩码机制。作为掩模机构的操作的结果，单元被传送到输出端口或被丢弃。两个交换系统组合在第一和第二交换机结构中，每个具有交换机核心和一组交换机核心接入层（SCAL）元件。每个SCAL元件分别包括SCAL接收元件和SCAL Xmit元件，用于允许访问一个交换系统的输入和输出端口。

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