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61. 发明授权

US08637963B2 Radiation-shielded semiconductor device 有权
标题翻译：辐射屏蔽半导体器件
公开(公告)号：US08637963B2
公开(公告)日：2014-01-28
申请号：US13253344
申请日：2011-10-05
申请人： Suresh Kumar Upadhyayula , Hem Takiar , Chih-Chin Liao
发明人： Suresh Kumar Upadhyayula , Hem Takiar , Chih-Chin Liao
IPC分类号： H01L23/552 , H01L21/70 , H01L23/495
CPC分类号： H01L23/3135 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/552 , H01L24/06 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2224/04042 , H01L2224/05554 , H01L2224/06155 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06537 , H01L2225/06562 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device is disclosed including an electromagnetic radiation shield. The device may include a substrate having a shield ring defined in a conductance pattern on a surface of the substrate. One or more semiconductor die may be affixed and electrically coupled to the substrate. The one or more semiconductor die may then be encapsulated in molding compound. Thereafter, a metal may be plated around the molding compound and onto the shield ring to form an EMI/RFI shield for the device.
摘要翻译：公开了一种包括电磁辐射屏蔽的半导体器件。该器件可以包括具有在衬底的表面上以导电图案限定的屏蔽环的衬底。可以将一个或多个半导体管芯固定并电耦合到衬底。然后可以将一个或多个半导体管芯封装在模制化合物中。此后，可以在模制化合物周围将金属镀在屏蔽环上，以形成该装置的EMI / RFI屏蔽。

62. 发明授权

US08653653B2 High density three dimensional semiconductor die package 有权
标题翻译：高密度三维半导体芯片封装
公开(公告)号：US08653653B2
公开(公告)日：2014-02-18
申请号：US12648697
申请日：2009-12-29
申请人： Cheeman Yu , Chih-Chin Liao , Hem Takiar
发明人： Cheeman Yu , Chih-Chin Liao , Hem Takiar
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/04 , G11C5/143 , G11C8/12 , H01L21/485 , H01L23/5382 , H01L25/50 , H01L2225/06527 , H01L2225/06579 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.
摘要翻译：公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如在带自动焊接工艺中使用的聚酰亚胺带。带可以具有多个重复图案的迹线和形成在其上的接触垫。每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在将图案从基板切割成对准和堆叠之后将一个图案的迹线粘合到另一图案的迹线。诸如闪速存储器和控制器管芯的半导体管芯安装在衬底上各个图案的迹线上。为了使控制器裸片独特地寻址堆叠中的特定闪存芯片，支持存储芯片的每个衬底上的一组迹线被用作地址引脚，并相对于其它衬底的迹线的布局以独特的布局冲压。通过在基板上提供具有唯一的地址迹线布局的每个闪速存储器半导体管芯，每个存储管芯可以被控制器管芯选择性地寻址。

63. 发明申请

US20100055836A1 METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA ELECTRICAL CONNECTORS EXTENDING BETWEEN ADJOINING SEMICONDUCTOR PACKAGES 有权
标题翻译：通过扩展半导体封装之间的电气连接器堆叠和互连半导体封装的方法
公开(公告)号：US20100055836A1
公开(公告)日：2010-03-04
申请号：US12614998
申请日：2009-11-09
申请人： Cheeman Yu , Chih-Chin Liao , Hem Takiar
发明人： Cheeman Yu , Chih-Chin Liao , Hem Takiar
IPC分类号： H01L21/56
CPC分类号： H01L24/49 , H01L23/3121 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49174 , H01L2224/49175 , H01L2224/73265 , H01L2224/92247 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2225/1064 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , Y10S438/977 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.
摘要翻译：公开了一种包括多个堆叠的半导体封装的电子部件。第一个这样的实施例包括用于电耦合堆叠的半导体封装的内部连接器。第二个这样的实施例包括用于电耦合堆叠的半导体封装的外部连接器。

64. 发明申请

US20130087895A1 RADIATION-SHIELDED SEMICONDUCTOR DEVICE 有权
标题翻译：辐射屏蔽半导体器件
公开(公告)号：US20130087895A1
公开(公告)日：2013-04-11
申请号：US13253344
申请日：2011-10-05
申请人： Suresh Kumar Upadhyayula , Hem Takiar , Chih-Chin Liao
发明人： Suresh Kumar Upadhyayula , Hem Takiar , Chih-Chin Liao
IPC分类号： H01L23/552 , H01L21/56 , H01L21/58
CPC分类号： H01L23/3135 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/552 , H01L24/06 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2224/04042 , H01L2224/05554 , H01L2224/06155 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06537 , H01L2225/06562 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device is disclosed including an electromagnetic radiation shield. The device may include a substrate having a shield ring defined in a conductance pattern on a surface of the substrate. One or more semiconductor die may be affixed and electrically coupled to the substrate. The one or more semiconductor die may then be encapsulated in molding compound. Thereafter, a metal may be plated around the molding compound and onto the shield ring to form an EMI/RFI shield for the device.
摘要翻译：公开了一种包括电磁辐射屏蔽的半导体器件。该器件可以包括具有在衬底的表面上以导电图案限定的屏蔽环的衬底。可以将一个或多个半导体管芯固定并电耦合到衬底。然后可以将一个或多个半导体管芯封装在模制化合物中。此后，可以在模制化合物周围将金属镀在屏蔽环上，以形成该装置的EMI / RFI屏蔽。

65. 发明申请

US20120193802A1 GLOB TOP SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：US20120193802A1
公开(公告)日：2012-08-02
申请号：US13019126
申请日：2011-02-01
申请人： Chin-Tien Chiu , Chih-Chin Liao , Peng Fu
发明人： Chin-Tien Chiu , Chih-Chin Liao , Peng Fu
IPC分类号： H01L23/48
CPC分类号： H01L23/24 , H01L21/56 , H01L23/3121 , H01L24/73 , H01L2224/05554 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/181 , H01L2924/00012
摘要： A semiconductor package is disclosed including a substrate, a solder mask layer, one or more semiconductor die mounted to the solder mask layer and electrically coupled to the substrate, and a glob top cover over the semiconductor die. The solder mask further includes a dam protruding above surrounding areas of the solder mask layer and a cavity recessed into the solder mask layer for limiting flow of the glob top cover when the glob top material is applied.
摘要翻译：公开了一种半导体封装，其包括衬底，焊接掩模层，安装到焊料掩模层并电耦合到衬底的一个或多个半导体管芯以及半导体管芯上的球顶盖。焊料掩模还包括突出在焊料掩模层的周围区域上方的坝体和凹入焊料掩模层中的空腔，用于限制球形顶盖材料施加时球体顶盖的流动。

66. 发明授权

US06570249B1 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US06570249B1
公开(公告)日：2003-05-27
申请号：US10060811
申请日：2002-01-30
申请人： Chih-Chin Liao , Han-PIng Pu , Chien-Ping Huang
发明人： Chih-Chin Liao , Han-PIng Pu , Chien-Ping Huang
IPC分类号： H01L2352
CPC分类号： H01L25/16 , H01L23/49575 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/0657 , H01L2224/05554 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48233 , H01L2224/48247 , H01L2224/48253 , H01L2224/49171 , H01L2924/01015 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19104 , H01L2924/19105 , H01L2924/19107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device and a fabrication method of the same are proposed, in which at least one electronic component is firstly mounted on a first substrate, and then the first substrate is attached onto a semiconductor chip or a second substrate. Further, with the chip being deposited on the second substrate, electrical connection is established among the first substrate, the second substrate and the chip. This combined structure is subsequently subjected to molding, ball implantation and singulation processes, and thus completes the fabrication of the semiconductor device. Such a semiconductor device provides significant advantages, including prevention of the occurrence of wire short-circuiting, no need to alter the substrate design, no need to use a circuit pattern with fine pitches or an expensive substrate integrated with electronic components.
摘要翻译：提出了一种半导体器件及其制造方法，其中至少一个电子部件首先安装在第一基板上，然后将第一基板附接到半导体芯片或第二基板上。此外，由于芯片沉积在第二基板上，所以在第一基板，第二基板和芯片之间建立电连接。随后对该组合结构进行模制，球注入和分割处理，从而完成半导体器件的制造。这样的半导体器件提供了显着的优点，包括防止线路短路的发生，不需要改变基板设计，不需要使用具有细间距的电路图案或与电子部件集成的昂贵的基板。

67. 发明授权

US06531762B1 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US06531762B1
公开(公告)日：2003-03-11
申请号：US09992993
申请日：2001-11-14
申请人： Chih-Chin Liao , Kuan-Cheng Chen
发明人： Chih-Chin Liao , Kuan-Cheng Chen
IPC分类号： H01L23495
CPC分类号： H01L24/48 , H01L23/49838 , H01L24/45 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32225 , H01L2224/45144 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/4911 , H01L2224/4912 , H01L2224/49171 , H01L2224/4943 , H01L2224/73265 , H01L2924/00014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package is proposed, in which a substrate is formed with a chip bonding area and a plurality of bond fingers surrounding the chip bonding area, and a plurality of bridging elements are disposed in a stagger manner between the chip bonding area and the bond fingers on the substrate. Multiple wire bonding processes are performed to bond first gold wires between the chip and the bridging elements, and bond second gold wires between the bridging elements and the bond fingers. This therefore significantly shortens a wire bonding distance as compared with only one time of wire bonding for electrically connecting the chip to the substrate. As a result, wire bond operability is improved, and the shortened wire bonding distance reduces wire length so as to enhance resistance of the gold wires to mold flow impact during molding, thereby preventing wire sweeping or wire sagging from occurrence.
摘要翻译：提出了一种半导体封装，其中衬底形成有芯片接合区域和围绕芯片接合区域的多个键合键，并且多个桥接元件以交错的方式设置在芯片接合区域和结合指状物之间在基板上。执行多引线接合工艺以将芯片和桥接元件之间的第一金线接合，并且将桥接元件和键合指之间的第二金线接合。因此，与用于将芯片电连接到衬底的引线接合的时间相比，这显着缩短了引线接合距离。结果，提高了引线接合可操作性，并且缩短的引线接合距离减小了线长度，从而提高了金线在成型过程中模具流动冲击的阻力，从而防止电线清扫或线下垂发生。

68. 发明授权

US06465891B2 Integrated-circuit package with a quick-to-count finger layout design on substrate 有权
标题翻译：集成电路封装，在基板上具有快速计数的手指布局设计
公开(公告)号：US06465891B2
公开(公告)日：2002-10-15
申请号：US09766476
申请日：2001-01-19
申请人： Wen-Hsin Wang , Chih-Chin Liao
发明人： Wen-Hsin Wang , Chih-Chin Liao
IPC分类号： H01L2348
CPC分类号： H01L24/49 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L2224/05554 , H01L2224/45144 , H01L2224/48237 , H01L2224/49171 , H01L2924/01005 , H01L2924/01006 , H01L2924/01079 , H01L2924/14 , H01L2924/00014
摘要： An integrated-circuit package with a quick-to-count finger layout design on substrate is proposed, which can help fabrication engineers to visually check the total number of fingers on the substrate in a quick and accurate manner. The proposed integrated-circuit package is characterized by the provision of a line-up array of fingers which includes a plurality of first-shape fingers partitioned equally in number into a plurality of subgroups; and a plurality of second-shape fingers, which are substantially visually distinguishable in outer appearance from the first-shape fingers, and which are interposed between adjacent subgroups of the first-shape fingers to serve as count tokens. This finger layout design allows the fabrication engineers to visually check the total number of the line-up array of fingers on the substrate simply by counting through the second-shape fingers that serve as count tokens and then multiply the result by the number of first-shape fingers in each subgroup plus one.
摘要翻译：提出了一种在基板上具有快速计数手指布局设计的集成电路封装，可以帮助制造工程师以快速准确的方式目视检查基板上的手指总数。所提出的集成电路封装的特征在于提供一个阵列阵列的指状阵列，其包括多个分成多个子组的数个等分的第一形状的指状物; 以及多个第二形状的手指，其在外观上与第一形状指状件基本上在视觉上可区分，并且被插入在第一形状指状物的相邻子组之间用作计数令牌。这种手指布局设计允许制造工程师通过仅通过用作计数令牌的第二形手指计数，然后将结果乘以第一形状的数量，目视地检查基板上的指状阵列的总数，每个子组中的形状手指加一个。

69. 发明授权

US06399417B1 Method of fabricating plated circuit lines over ball grid array substrate 失效
标题翻译：在球栅阵列基板上制造电镀电路线的方法
公开(公告)号：US06399417B1
公开(公告)日：2002-06-04
申请号：US09837959
申请日：2001-04-19
申请人： Wen Cheng Lee , Chih-Chin Liao
发明人： Wen Cheng Lee , Chih-Chin Liao
IPC分类号： H01L2144
CPC分类号： H05K3/242 , H01L21/4846 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H05K3/0047 , H05K2203/1572 , H05K2203/175 , H01L2924/00014
摘要： A method is proposed for the fabrication of plated circuit lines, including contact fingers, electrically-conductive traces, and solder-ball pads, over an BGA (Ball Grid Array) substrate. The method is characterized by that contact fingers, electrically-conductive traces, and solder-ball pads on the BGA substrate are interconnected with provisional bridging lines; and then, each integrally-connected group of the contact fingers, the electrically-conductive traces, and the solder-ball pads is connected via a branched plating line to a common plating bus. During plating process, the plating electrical current can be applied to the plating bus and then distributed over these branched plating lines to all of the contact fingers and the solder-ball pads. Finally, a drilling process is performed to break all the provisional bridging lines into open-circuited state. Compared to the prior art, since the proposed method requires no use of etchant during the drilling process, it would cause no contamination to the substrate surfaces. Moreover, the proposed method allows the use of a reduced layout area for the circuit lines and can help reduce mutual inductive interference among the circuit lines.
摘要翻译：提出了一种用于在BGA（球栅阵列）衬底上制造包括接触指状物，导电迹线和焊球焊盘的电镀电路线的方法。该方法的特征在于，BGA衬底上的接触指状物，导电迹线和焊球焊盘与临时桥接线互连; 然后，每个整体连接的接触指的组，导电迹线和焊球焊盘通过分支电镀线连接到公共电镀母线。在电镀过程中，电镀电流可以施加到电镀母线上，然后分布在这些分支电镀线上，到所有接触指和焊球垫。最后，进行钻井过程以将所有临时桥接线路断开为断路状态。与现有技术相比，由于所提出的方法在钻井过程中不需要使用蚀刻剂，因此不会对基材表面产生污染。此外，所提出的方法允许对电路线路使用减少的布局面积，并且可以帮助减少电路线路之间的互感干扰。

70. 发明申请

US20120025396A1 SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED DIE AND EFFICIENT WIRE BONDING 有权
标题翻译：具有DIE堆叠布置的半导体器件，包括插入式和有效的电线接合
公开(公告)号：US20120025396A1
公开(公告)日：2012-02-02
申请号：US12844959
申请日：2010-07-28
申请人： Chih-Chin Liao , Cheeman Yu , Ya Huei Lee
发明人： Chih-Chin Liao , Cheeman Yu , Ya Huei Lee
IPC分类号： H01L23/488
CPC分类号： H01L23/49822 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/4569 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/4917 , H01L2224/49171 , H01L2224/49175 , H01L2224/49433 , H01L2224/73265 , H01L2224/85207 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package.
摘要翻译：公开了一种半导体管芯封装。半导体封装的示例包括散布有第二组半导体管芯的第一组半导体管芯。来自第一组和第二组的模具沿着第一轴线彼此偏移并且沿着与第一轴线正交的第二轴线相对于彼此交错。半导体封装的第二示例包括不规则形状的边缘和从封装中的最低半导体管芯上方的半导体管芯到基板的引线接合。

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