专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20100164001A1 Implant process for blocked salicide poly resistor and structures formed thereby 审中-公开
标题翻译：植入过程中封闭的自杀化合物多晶硅电阻和结构形成
公开(公告)号：US20100164001A1
公开(公告)日：2010-07-01
申请号：US12319015
申请日：2008-12-30
申请人： Joodong Park , Chia-Hong Jan , Lisa M. McGill
发明人： Joodong Park , Chia-Hong Jan , Lisa M. McGill
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/22
CPC分类号： H01L21/26506 , H01L21/26513 , H01L27/0629 , H01L28/24 , H01L29/665 , H01L29/66575
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include implanting an exposed p type silicon portion of a substrate with a carbon species, wherein endcap regions of a blocked salicide resistor and a p type structure that are both disposed on the exposed p type silicon portion of the substrate are implanted with the carbon species.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括用碳物种植入衬底的暴露的p型硅部分，其中嵌入在衬底的暴露的p型硅部分上的封闭的自对夹硅电阻器和ap型结构的端盖区域被植入碳种类。

62. 发明申请

US20100163952A1 Flash Cell with Integrated High-K Dielectric and Metal-Based Control Gate 审中-公开
标题翻译：具有集成高K介质和金属控制门的闪存单元
公开(公告)号：US20100163952A1
公开(公告)日：2010-07-01
申请号：US12347904
申请日：2008-12-31
申请人： Chia-Hong Jan , Walid M. Hafez
发明人： Chia-Hong Jan , Walid M. Hafez
IPC分类号： H01L29/66 , H01L21/336 , H01L21/04 , H01L29/41
CPC分类号： H01L27/11521 , H01L29/40114 , H01L29/42324 , H01L29/7881
摘要： A semiconductor device is described having an integrated high-k dielectric layer and metal control gate. A method of fabricating the same is described. Embodiments of the semiconductor device include a high-k dielectric layer disposed on a floating gate. The high-k dielectric layer defines a recess. A metal control gate is formed in the recess.
摘要翻译：描述了具有集成的高k电介质层和金属控制栅极的半导体器件。对其制造方法进行说明。半导体器件的实施例包括设置在浮置栅极上的高k电介质层。高k电介质层限定凹陷。金属控制门形成在凹槽中。

63. 发明申请

US20090170273A1 Dual layer hard mask for block salicide poly resistor (BSR) patterning 失效
标题翻译：双层硬掩模用于块状硅化物电阻（BSR）图案化
公开(公告)号：US20090170273A1
公开(公告)日：2009-07-02
申请号：US12005944
申请日：2007-12-27
申请人： Joodong Park , Chia-Hong Jan , Paul Reese
发明人： Joodong Park , Chia-Hong Jan , Paul Reese
IPC分类号： H01L21/02
CPC分类号： H01L29/8605 , H01L28/24
摘要： In general, in one aspect, a method includes forming a semiconductor substrate having an N+ diffusion region, a shallow trench isolation (STI) region adjacent to the N+ diffusion region, and a blocked salicide poly resistor (BSR) region over the STI region. An oxide layer is over the substrate. A nitride layer is formed over the oxide layer and is annealed. A resist layer is patterned on the annealed nitride layer, wherein the resist layer covers a portion of the BSR region. The annealed nitride layer is etched using the resist layer as a pattern. The resist layer is removed and the oxide layer is etched using the annealed nitride layer as a pattern. Germanium pre-amorphization is implanted into the substrate, wherein the oxide and the annealed nitride layers protect a portion of the BSR region from the implanting.
摘要翻译：通常，在一个方面，一种方法包括形成具有N +扩散区域，与N +扩散区域相邻的浅沟槽隔离（STI）区域和在STI区域上的封闭的自对准硅化物多晶硅电阻器（BSR）区域的半导体衬底。氧化物层在衬底上。在氧化物层上形成氮化物层并进行退火。在退火的氮化物层上图案化抗蚀剂层，其中抗蚀剂层覆盖BSR区域的一部分。使用抗蚀剂层作为图案蚀刻退火的氮化物层。去除抗蚀剂层，并使用退火的氮化物层作为图案来蚀刻氧化物层。将锗预非晶化植入衬底中，其中氧化物和退火的氮化物层保护BSR区域的一部分免受植入。

64. 发明授权

US07436035B2 Method of fabricating a field effect transistor structure with abrupt source/drain junctions 有权
标题翻译：制造具有突然的源极/漏极结的场效应晶体管结构的方法
公开(公告)号：US07436035B2
公开(公告)日：2008-10-14
申请号：US10917722
申请日：2004-08-12
申请人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
发明人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
IPC分类号： H01L29/72
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/2022 , H01L29/0646 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66477 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.
摘要翻译：体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。凹部包括在栅极结构的一部分下面的横向延伸的区域。这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。替代实施例可以用单导电类型的后填充凹槽来实现。

65. 发明授权

US06765273B1 Device structure and method for reducing silicide encroachment 失效
公开(公告)号：US06765273B1
公开(公告)日：2004-07-20
申请号：US09115405
申请日：1998-07-14
申请人： Robert S. Chau , Ebrahim Andideh , Mitch C. Taylor , Chia-Hong Jan , Julie Tsai
发明人： Robert S. Chau , Ebrahim Andideh , Mitch C. Taylor , Chia-Hong Jan , Julie Tsai
IPC分类号： H01L2976
CPC分类号： H01L29/66515 , H01L21/28525 , H01L21/28562 , H01L21/823814 , H01L21/823835 , H01L21/823878 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

66. 发明授权

US06518155B1 Device structure and method for reducing silicide encroachment 失效
公开(公告)号：US06518155B1
公开(公告)日：2003-02-11
申请号：US08884912
申请日：1997-06-30
申请人： Robert S. Chau , Ebrahim Andideh , Mitch C. Taylor , Chia-Hong Jan , Julie Tsai
发明人： Robert S. Chau , Ebrahim Andideh , Mitch C. Taylor , Chia-Hong Jan , Julie Tsai
IPC分类号： H01L213205
CPC分类号： H01L29/66515 , H01L21/28525 , H01L21/28562 , H01L21/823814 , H01L21/823835 , H01L21/823878 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

67. 发明授权

US06198142B1 Transistor with minimal junction capacitance and method of fabrication 失效
标题翻译：具有最小结电容的晶体管和制造方法
公开(公告)号：US06198142B1
公开(公告)日：2001-03-06
申请号：US09127349
申请日：1998-07-31
申请人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
发明人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
IPC分类号： H01L2976
CPC分类号： H01L29/66636 , H01L21/26533 , H01L29/0653 , H01L29/165 , H01L29/665 , H01L29/66537 , H01L29/7834
摘要： A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.
摘要翻译：在该制造方法中具有最小结电容的新型MOS晶体管。根据本发明，在半导体衬底的第一表面上形成栅介质层。然后在栅极电介质层上形成栅电极。接下来，在栅电极的相对侧上的半导体衬底中形成一对凹部。然后在每个凹部的表面上形成介电层。然后将半导体材料沉积到凹槽中以形成一对源极/漏极区域。

68. 发明授权

US5908313A Method of forming a transistor 失效
标题翻译：形成晶体管的方法
公开(公告)号：US5908313A
公开(公告)日：1999-06-01
申请号：US775410
申请日：1996-12-31
申请人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
发明人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
IPC分类号： H01L21/225 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/417 , H01L29/49
CPC分类号： H01L29/66477 , H01L21/26586 , H01L21/28052 , H01L29/0653 , H01L29/1083 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66628 , H01L29/66636 , H01L21/2254 , H01L21/2257 , H01L21/26506
摘要： A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.
摘要翻译：在该制造方法中具有最小结电容的新型MOS晶体管。根据本发明，在半导体衬底的第一表面上形成栅介质层。然后在栅极电介质层上形成栅电极。接下来，在栅电极的相对侧上的半导体衬底中形成一对凹部。然后在每个凹部的表面上形成介电层。然后将半导体材料沉积到凹槽中以形成一对源极/漏极区域。

69. 发明授权

US5516725A Process for preparing schottky diode contacts with predetermined barrier heights 失效
标题翻译：制备具有预定屏障高度的肖特基二极管触点的工艺
公开(公告)号：US5516725A
公开(公告)日：1996-05-14
申请号：US85622
申请日：1993-06-30
申请人： Y. Austin Chang , Chia-Hong Jan , Chia-Ping Chen
发明人： Y. Austin Chang , Chia-Hong Jan , Chia-Ping Chen
IPC分类号： C22C5/04 , C22C19/00 , C23C14/14 , C23C14/18 , C23C14/34 , H01L21/28 , H01L21/285 , H01L21/768 , H01L23/522 , H01L29/40 , H01L29/47 , H01L21/44
CPC分类号： C23C14/185 , C22C19/00 , C22C5/04 , H01L29/475 , H01L2924/0002
摘要： A process is provided for producing a Schottky diode having a preselected barrier height .phi..sub.Bn. The substrate is preferably n-GaAs, the metallic contact is derived from a starting alloy of the Formula [.SIGMA.M.sub..delta. ](Al.sub.x Ga.sub.1-x) wherein: .SIGMA.M is a moiety which consists of at least one M, and when more than one M is present, each M is different, M is a Group VIII metal selected from the group consisting of nickel, cobalt, ruthenium, rhodium, indium and platinum, .delta. is a stoichiometric coefficient whose total value in any given .SIGMA.M moiety is 1, and x is a positive number between 0 and 1 (that is, x ranges from greater than 0 to less than 1). Also, the starting alloy is capable of forming with the substrate a two phase equilibrium reciprocal system of the binary alloy mixture [.SIGMA.M.sub..delta. ]Ga-[.SIGMA.M.sub..delta. ]Al-AlAs-GaAs. When members of an alloy subclass within this Formula are each preliminarily correlated with the barrier height .phi..sub.Bn of a contact producable therewith, then Schottky diodes of predetermined barrier heights are producable by sputtering and annealing. Further provided are the product Schottky diodes that are produced according to this process.
摘要翻译：提供了一种制备具有预先选择的势垒高度phi Bn的肖特基二极管的工艺。衬底优选为n-GaAs，金属接触源自式[SIGMA Mδ]（Al x Ga 1-x）的起始合金，其中：SIGMA M是由至少一个M组成的部分，并且当多于一个 M存在，每个M不同，M是选自镍，钴，钌，铑，铟和铂的Ⅷ族金属，δ是任何给定的SIGMA M部分的总值为1的化学计量系数， x是0和1之间的正数（即x大于0到小于1）。此外，起始合金能够与基板一起形成二元合金混合物[SIGMA Mδ] Ga - [SIGMA M] Al-AlAs-GaAs的两相平衡互易系统。当该式中的合金子类的成员各自与可生产的接触层的势垒高度phi Bn初步相关时，则可以通过溅射和退火产生预定的屏障高度的肖特基二极管。还提供了根据该方法生产的肖特基二极管产品。

70. 发明授权

US09640634B2 Field effect transistor structure with abrupt source/drain junctions 有权
公开(公告)号：US09640634B2
公开(公告)日：2017-05-02
申请号：US12700637
申请日：2010-02-04
申请人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
发明人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
IPC分类号： H01L21/336 , H01L29/66 , H01L29/08 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/417 , H01L29/49 , H01L29/78 , H01L21/20
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/2022 , H01L29/0646 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66477 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式