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61. 发明授权

US07624366B2 Clock aware placement 失效
标题翻译：时钟感知放置
公开(公告)号：US07624366B2
公开(公告)日：2009-11-24
申请号：US11554637
申请日：2006-10-31
申请人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.
摘要翻译：锁存器在公共时钟域中的布局被有效优化，以缩小域的物理大小，同时保持时序要求。锁存器优选地使用二次放置放置在第一布局中，并且构建代表中间时钟结构的星形物体。锁存器根据与星形物体源的线距离进行加权，然后使用加权重新放置。可以迭代地重复加权放置和重新分配，直到达到目标数量的箱。最终全局放置中的锁存器的边界用于定义移动以进一步详细放置。

62. 发明申请

US20090193376A1 CLOCK POWER MINIMIZATION WITH REGULAR PHYSICAL PLACEMENT OF CLOCK REPEATER COMPONENTS 失效
标题翻译：时钟功率最小化与定时重放组件的正常放置
公开(公告)号：US20090193376A1
公开(公告)日：2009-07-30
申请号：US12022849
申请日：2008-01-30
申请人： Charles J. Alpert , Ruchir Puri , Shyam Ramji , Ashish K. Singh , Chin Ngai Sze
发明人： Charles J. Alpert , Ruchir Puri , Shyam Ramji , Ashish K. Singh , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/62
摘要： Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures.
摘要翻译：电源，路由和电迁移已成为现代微处理器设计中的关键问题。在高性能设计中，时钟是功耗最大的消费者。排列时钟元件的规律性，以便最小化时钟网络上的电容可以帮助降低时钟功率，但是，由于物理放置这些组件的一些灵活性可能会损害性能。本发明提供了以规则方式最佳地放置时钟组件以便在性能约束内最小化时钟功率的技术。创建矩形网格，并将时钟分配结构分配给网格交点。然后锁存器位于时钟分布结构周围，以最小化锁存器和相应时钟分配结构之间的连接的总距离。可以独立地调整网格的水平和垂直间距以实现时钟分配结构的更均匀的扩展。

63. 发明申请

US20080127018A1 Clock Aware Placement 失效
标题翻译：时钟感知放置
公开(公告)号：US20080127018A1
公开(公告)日：2008-05-29
申请号：US11554637
申请日：2006-10-31
申请人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
发明人： Charles J. Alpert , David J. Hathaway , William R. Migatz , Gi-Joon Nam , Haoxing Ren , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.
摘要翻译：锁存器在公共时钟域中的布局被有效优化，以缩小域的物理大小，同时保持时序要求。锁存器优选地使用二次放置放置在第一布局中，并且构建代表中间时钟结构的星形物体。锁存器根据与星形物体源的线距离进行加权，然后使用加权重新放置。可以迭代地重复加权放置和重新分配，直到达到目标数量的箱。最终全局放置中的锁存器的边界用于定义移动以进一步详细放置。

64. 发明申请

US20070283301A1 System and Method of Eliminating Electrical Violations 审中-公开
标题翻译：消除电气违规的制度和方法
公开(公告)号：US20070283301A1
公开(公告)日：2007-12-06
申请号：US11422174
申请日：2006-06-05
申请人： Arvind K. Karandikar , Charles J. Alpert , Mehmet C. Yildiz , Stephen T. Quay , Tuhin Mahmud , Paul G. Villarrubia
发明人： Arvind K. Karandikar , Charles J. Alpert , Mehmet C. Yildiz , Stephen T. Quay , Tuhin Mahmud , Paul G. Villarrubia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081 , G06F17/5045
摘要： A system and method for correcting electrical violations, the method including examining a plurality of nets for at least one electrical violation in a sequential order of a first output-to-input traversal, and determining a net correction in each net of the plurality of nets having an electrical violation prior to examining a next net in the sequential order of the first output-to-input traversal.
摘要翻译：一种用于校正电气违规的系统和方法，所述方法包括以第一输出到输入遍历的顺序检查多个网络中的至少一个电气违规，以及确定多个网络的每个网络中的净校正在按照第一输出到输入遍历的顺序检查下一个网络之前具有电气违规。

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