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    • 61. 发明授权
    • Slide type mobile terminal and sliding mechanism thereof
    • 滑动型移动终端及其滑动机构
    • US07630744B2
    • 2009-12-08
    • US11614639
    • 2006-12-21
    • Jin-Ho Lee
    • Jin-Ho Lee
    • H04M1/00
    • H04M1/0237
    • In accordance with one aspect of the invention, a slide type mobile terminal comprises a first body; a second body slidably installed on the first body; and a sliding mechanism installed between the first body and the second body for guiding a slide motion of the second body in relation to the first body such that the second body automatically slides over a substantial portion of the first body after the second body slides over a first portion of the first body by way of exertion of external force.
    • 根据本发明的一个方面,滑盖型移动终端包括第一主体; 可滑动地安装在第一主体上的第二主体; 以及安装在所述第一主体和所述第二主体之间的滑动机构,用于相对于所述第一主体引导所述第二主体的滑动运动,使得所述第二主体在所述第二主体滑过第一主体之后自动地滑过所述第一主体的主要部分 第一部分的第一部分通过外力的作用。
    • 65. 发明授权
    • Slide type mobile terminal and sliding mechanism thereof
    • 滑动型移动终端及其滑动机构
    • US07158818B2
    • 2007-01-02
    • US10977184
    • 2004-10-28
    • Jin-Ho Lee
    • Jin-Ho Lee
    • H04M1/00
    • H04M1/0237
    • In accordance with one aspect of the invention, a slide type mobile terminal comprises a first body; a second body slidably installed on the first body; and a sliding mechanism installed between the first body and the second body for guiding a slide motion of the second body in relation to the first body such that the second body automatically slides over a substantial portion of the first body after the second body slides over a first portion of the first body by way of exertion of external force.
    • 根据本发明的一个方面,滑盖型移动终端包括第一主体; 可滑动地安装在第一主体上的第二主体; 以及安装在所述第一主体和所述第二主体之间的滑动机构,用于相对于所述第一主体引导所述第二主体的滑动运动,使得所述第二主体在所述第二主体滑过第一主体之后自动地滑过所述第一主体的主要部分 第一部分的第一部分通过外力的作用。
    • 68. 发明授权
    • Data transmission circuit for compensating difference of speed
    • 用于补偿速度差的数据传输电路
    • US06310504B1
    • 2001-10-30
    • US09765517
    • 2001-01-19
    • Young-Ho SuhJin-Ho Lee
    • Young-Ho SuhJin-Ho Lee
    • H03H1126
    • H04L25/028H03K19/00323
    • A data transmission circuit is provided for compensating for a difference between data transmission speed occurring at start and end portions of a data line. The circuit minimizes a time delay caused by resistance/capacitance loading of the data line through which data is transmitted, thereby improving data transmission speed. The data transmission circuit of the present invention includes a compensation circuit to compensate for the time delay between the data signals at the start and end portions of the data line. The compensation circuit is adapted to amplify and rapidly develop a data signal at the end portion of the data line through which a data signal is enabled from its high state to its low state and transmitted as a data signal at the end portion of the data line.
    • 提供了一种数据传输电路,用于补偿在数据线的开始和结束部分发生的数据传输速度之间的差异。 该电路最小化由传输数据的数据线的电阻/电容负载引起的时间延迟,从而提高数据传输速度。 本发明的数据传输电路包括补偿电路,用于补偿数据线的起始和终止部分之间的数据信号之间的时间延迟。 补偿电路适于在数据线的端部放大并快速地形成数据信号,数据信号通过该数据信号从其高状态到低状态,并作为数据信号发送到数据线的端部 。
    • 69. 发明授权
    • Integrated circuit memory devices having main and section row decoders
for providing improved burst mode operation
    • 具有主和部分行解码器的集成电路存储器件,用于提供改进的突发模式操作
    • US5859802A
    • 1999-01-12
    • US986742
    • 1997-12-08
    • Jin-Ho LeeHee-Chul Pack
    • Jin-Ho LeeHee-Chul Pack
    • G11C11/41G11C8/04G11C11/401G11C11/407G11C11/413G11C29/00G11C29/04G11C7/00
    • G11C29/84G11C8/04
    • Integrated circuit memory devices having improved burst mode operation include an array of memory cells arranged as a plurality of normal rows of memory cells electrically coupled to respective normal section word lines (SWL) and a plurality of redundant rows of memory cells electrically coupled to respective redundant section word lines (RSWL). A first normal section row decoder is also provided. The first normal section row decoder has first inputs electrically coupled to a plurality of burst address selection lines (Ci, Cj, Ck and Cl), a second input electrically coupled to a normal main word line (MWL) and outputs electrically coupled to a plurality of the normal section word lines (SWL1-4). A first redundancy section row decoder is also preferably provided. The first redundancy section row decoder has first inputs electrically coupled to the plurality of burst address selection lines, a second input electrically coupled to a redundant main word line (RMWL) and outputs electrically coupled to a plurality of the redundant section word lines (RSWL1-4). Normal main row decoder circuitry is also provided and is responsive to a most significant portion of a row address. When the appropriate portion of a predetermined row address is provided, the main row decoder circuitry drives the corresponding normal main word line. Moreover, redundant main row decoder circuitry is provided and is responsive to the most significant portion of the row address. When the appropriate portion of a predetermined row address is provided, the redundant main row decoder circuitry drives the corresponding redundant main word line.
    • 具有改进的突发模式操作的集成电路存储器件包括布置为电耦合到相应的正常部分字线(SWL)的多个正常行的存储器单元的存储器单元的阵列和电耦合到相应冗余的多个冗余行的存储器单元 段字线(RSWL)。 还提供了第一正常段行解码器。 第一正常段行解码器具有电耦合到多个突发地址选择线(Ci,Cj,Ck和C1)的第一输入,电耦合到正常主字线(MWL)的第二输入,并且电耦合到多个 的正常段字线(SWL1-4)。 还优选地提供第一冗余部分行解码器。 第一冗余部分行解码器具有电耦合到多个突发地址选择线的第一输入,电耦合到冗余主字线(RMWL)的第二输入,并且电耦合到多个冗余部分字线(RSWL1- 4)。 还提供正常的主行解码器电路并且响应于行地址的最重要部分。 当提供预定行地址的适当部分时,主行解码器电路驱动相应的正常主字线。 此外,提供冗余主行解码器电路并且响应于行地址的最高有效部分。 当提供预定行地址的适当部分时,冗余主行解码器电路驱动相应的冗余主字线。