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61. 发明申请

WO2008033686A2 ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING A REDUCED NUMBER OF QUANTIZER OUTPUT LEVELS 审中-公开
标题翻译：模数转换器（ADC）具有减少数量的量测器输出电平
公开(公告)号：WO2008033686A2
公开(公告)日：2008-03-20
申请号：PCT/US2007/077363
申请日：2007-08-31
申请人： CIRRUS LOGIC, INC.
发明人： MELANSON, John, L.
IPC分类号： H03M3/04
CPC分类号： H03M3/412 , H03M3/424 , H03M3/452 , H03M3/454
摘要： An analog-to-digital converter provides for reduced complexity and power consumption along with improved linearity. The analog-to-digital converter has a reduced number of quantizer output levels and includes a loop filter, a quantizer for quantizing the output of the loop filter and a digital integrator for integrating the output of the quantizer. A difference circuit is included in the converter that produces a signal proportional to the difference between the present value and a previous value of the digital integrator output and provides feedback to the loop filter. The number of levels of the quantizer output is thereby reduced with respect to the modulator output, since the quantizer is operating on a feedback signal that represents changes in the output of the converter modulator rather than the modulator output itself.
摘要翻译：模数转换器提供降低的复杂性和功耗以及改进的线性度。模数转换器具有减少的量化器输出电平数量，并且包括环路滤波器，用于量化环路滤波器的输出的量化器和用于积分量化器的输出的数字积分器。差分电路包括在转换器中，产生与当前值和数字积分器输出的先前值之间的差成比例的信号，并向环路滤波器提供反馈。量化器输出的电平数量因此相对于调制器输出而减少，因为量化器在表示转换器调制器的输出的变化而不是调制器输出本身的反馈信号上操作。

62. 发明申请

WO2007067849A2 EXTENDED DYNAMIC RANGE CONSECUTIVE EDGE MODULATION (CEM) METHOD AND APPARATUS 审中-公开
标题翻译：扩展动态范围调整边缘调制（CEM）方法和设备
公开(公告)号：WO2007067849A2
公开(公告)日：2007-06-14
申请号：PCT/US2006/061096
申请日：2006-11-20
申请人： CIRRUS LOGIC, INC.
发明人： MELANSON, John, L.
IPC分类号： H03M3/04 , H03M7/36
CPC分类号： H03M7/3013 , H03M3/506 , H03M7/3026 , H03M7/3037
摘要： A consecutive edge modulation (CEM) method and apparatus provides improved dynamic range in a noise-shaped CEM pulse generator. A limiting circuit is provided to adjust the rising and trailing edge pulse portion widths to correct conditions where a minimum high-state or low-state pulse width would be violated by the commanded output value of the noise-shaping modulator. The adjusting circuit delays the rising edge of the next pulse if the minimum low state pulse width would not be met and/or extends the falling edge portion of the next pulse if the minimum high-state pulse width would not be met. The modulation range may be wider than typically possible for linear operation and may be set to ranges exceeding one- hundred percent modulation. The adjusting circuit overrides commanded modulation values during a next pulse if combination with the previous pulse will cause violation of a minimum pulse width.
摘要翻译：连续边缘调制（CEM）方法和装置在噪声形CEM脉冲发生器中提供改进的动态范围。提供限制电路以调整上升沿和下降沿脉冲部分宽度，以校正由噪声整形调制器的命令输出值违反最小高状态或低态脉冲宽度的条件。如果最小的低状态脉冲宽度不满足，则调整电路会延迟下一个脉冲的上升沿，和/或如果不满足最小的高状态脉冲宽度，则延迟下一个脉冲的下降沿部分。调制范围可能比线性操作通常可能的更宽，并且可以设置为超过百分之百调制的范围。如果与先前脉冲的组合将导致违反最小脉冲宽度，则调整电路在下一个脉冲期间覆盖命令的调制值。

63. 发明申请

WO2018161024A1 DIGITAL PWM MODULATOR 审中-公开
公开(公告)号：WO2018161024A1
公开(公告)日：2018-09-07
申请号：PCT/US2018/020749
申请日：2018-03-02
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZHANG, Lingli , CHENG, Frank , ZHU, Lei , LARSEN, Christian , MELANSON, John, L.
发明人： ZHANG, Lingli , CHENG, Frank , ZHU, Lei , LARSEN, Christian , MELANSON, John, L.
IPC分类号： H03F3/183 , H03F3/217
摘要： An improved Class-D amplifier may include a digital PWM modulator that receives a digital audio signal and that provides a PWM signal as an input to an analog PWM modulator of the Class-D amplifier. A digital PWM modulator may be configured to receive a digital signal and to generate a first PWM signal based on the digital signal. A digital PWM driver may be coupled to the digital PWM modulator. The digital PWM driver may be configured to receive the first PWM signal and to generate a reference PWM signal based on the first PWM signal. An analog PWM modulator may be coupled to the digital PWM driver. The analog PWM modulator may be configured to receive the reference PWM signal and to generate an output PWM signal based on the reference PWM signal.

64. 发明申请

WO2017196379A1 NON-LINEARITY CANCELLATION IN A DUAL-PATH ADC 审中-公开
标题翻译：双路ADC中的非线性消除
公开(公告)号：WO2017196379A1
公开(公告)日：2017-11-16
申请号：PCT/US2016/038277
申请日：2016-06-19
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZANBAGHI, Ramin , MORTAZAVI, Yousof , BRENNAN, Aaron , MELANSON, John, L.
发明人： ZANBAGHI, Ramin , MORTAZAVI, Yousof , BRENNAN, Aaron , MELANSON, John, L.
IPC分类号： H03M1/10 , H03M1/18 , H03M1/60
CPC分类号： H03M1/0602 , G10L19/00 , H03M1/1004 , H03M1/1038 , H03M1/1042 , H03M1/188 , H03M1/60
摘要： The overall performance of a dual-path ADC system may be improved by using a VCO-based ADC for small-amplitude signals and employing non-linear cancelation to remove nonlinearities in signals output by the VCO-based ADC. In particular, VCO-based dual-path ADC systems of this disclosure may be configured to receive a first digital signal from a first ADC and a second digital signal from a second ADC, wherein the second digital signal is more non-linear than the first digital signal. The dual-path systems may also be configured to determine one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals. The dual-path systems may be further configured to modify the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.
摘要翻译：双路ADC系统的整体性能可以通过使用基于VCO的ADC用于小幅度信号并采用非线性消除来消除基于VCO的输出信号中的非线性来改善 ADC。具体而言，本公开的基于VCO的双路径ADC系统可以被配置为接收来自第一ADC的第一数字信号和来自第二ADC的第二数字信号，其中第二数字信号比第一数字信号更为非线性数字信号。双路径系统还可以被配置为至少部分地基于第一和第二数字信号的处理来确定第二数字信号的一个或多个非线性系数。双路径系统可以进一步被配置为至少部分地基于所确定的一个或多个非线性系数来修改第二数字信号以生成更线性的第二数字信号。

65. 发明申请

WO2017030839A1 DUAL PROCESSING PATHS FOR DIFFERENTIAL MODE AND COMMON MODE SIGNALS FOR AN ADAPTABLE ANALOG-TO-DIGITAL CONVERTER (ADC) TOPOLOGY 审中-公开
标题翻译：用于适应模数转换器（ADC）拓扑学的差分模式和共模信号的双处理模式
公开(公告)号：WO2017030839A1
公开(公告)日：2017-02-23
申请号：PCT/US2016/046194
申请日：2016-08-09
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZANBAGHI, Ramin , MORTAZAVI, Yousof , BRENNAN, Aaron , MELANSON, John, L.
发明人： ZANBAGHI, Ramin , MORTAZAVI, Yousof , BRENNAN, Aaron , MELANSON, John, L.
IPC分类号： H03M1/12 , H03M3/00 , H04R19/04
CPC分类号： H03M1/14 , G06F3/16 , G11C27/024 , H03F3/005 , H03F3/45475 , H03F3/45959 , H03F2203/45421 , H03F2203/45512 , H03F2203/45544 , H03F2203/45551 , H03M1/124 , H03M1/1295 , H03M3/458 , H03M3/494 , H03M3/496 , H04R3/00 , H04R19/04 , H04R29/004 , H04R2499/11
摘要： One method of processing microphone input in an ADC to determine microphone configuration is to process the microphone input signals in two processing paths, in which one processing path processes a difference between differential input signals and another processing path processes an average value of the differential input signals. The outputs of these processing paths may be combined to generate a digital signal representative of the analog signal from the microphone. The digital signal contains a digital version of the audio in the environment around the microphone, but may also be used to detect microphone topology and configure aspects of the processing paths to match the detected microphone topology. An apparatus for an ADC may implement the two processing paths as two delta-sigma modulator loops.
摘要翻译：在ADC中处理麦克风输入以确定麦克风配置的一种方法是在两个处理路径中处理麦克风输入信号，其中一个处理路径处理差分输入信号之间的差异和另一个处理路径处理差分输入信号的平均值。这些处理路径的输出可以被组合以产生表示来自麦克风的模拟信号的数字信号。数字信号包含麦克风周围环境中的音频的数字版本，但也可用于检测麦克风拓扑并配置处理路径的各个方面以匹配检测到的麦克风拓扑结构。用于ADC的装置可以将两个处理路径实现为两个Δ-Σ调制器环路。

66. 发明申请

WO2016187479A1 RING FREQUENCY DIVIDER 审中-公开
标题翻译：环形分频器
公开(公告)号：WO2016187479A1
公开(公告)日：2016-11-24
申请号：PCT/US2016/033370
申请日：2016-05-19
申请人： CIRRUS LOGIC INTRNATIONAL SEMICONDUCTOR LTD. , MELANSON, John, L. , MORTAZAVI, Yousof , BRENNAN, Aaron
发明人： MELANSON, John, L. , MORTAZAVI, Yousof , BRENNAN, Aaron
IPC分类号： H03K3/03
CPC分类号： H03K23/54 , G04F10/02 , H03K3/0315 , H03K3/0372 , H03L7/0891 , H03L7/0995 , H03M1/50
摘要： A circuit for a divider or counter may include a frequency divider (200) having multiple rings (210, 220, 230) for dividing an input frequency (Vin, 202) to obtain an output frequency. The first and second rings (210, 220) may include an odd-numbered plurality of elements, such as inverters, wherein each inverter of a ring is coupled to another inverter of the ring in a circular chain. An input frequency (Vin, 202) may be input to a power supply input of inverters (212A- N) of the first ring (210). The second ring inverters (222A-N) may be coupled at a power supply input to output nodes of the first ring inverters, which results in the second ring operating at a divisional rate of the first frequency given by (N-l), where N is the number of inverters in the ring. The circuits may be used in frequency dividers and counters, such as in phase-locked loops (PLLs) and analog-to- digital converters (ADCs).
摘要翻译：用于分频器或计数器的电路可以包括具有用于分频输入频率（Vin，202）以获得输出频率的多个环（210,220,230）的分频器（200）。第一和第二环（210,220）可以包括奇数多个元件，例如逆变器，其中环的每个反相器以环形链耦合到环的另一个反相器。输入频率（Vin，202）可以被输入到第一环（210）的反相器（212A-N）的电源输入端。第二环形反相器（222A-N）可以在电源输入处耦合到第一环形逆变器的输出节点，这导致第二环以由（N1）给出的第一频率的分割速率操作，其中N是环中的逆变器数量。这些电路可用于分频器和计数器，例如锁相环（PLL）和模数转换器（ADC）。

67. 发明申请

WO2016032598A2 LOW-POWER ANALOG-TO-DIGITAL CONVERTER FOR SENSING GEOPHONE SIGNALS 审中-公开
标题翻译：低功耗模拟至数字转换器，用于检测地理信号
公开(公告)号：WO2016032598A2
公开(公告)日：2016-03-03
申请号：PCT/US2015/036151
申请日：2015-06-17
申请人： CIRRUS LOGIC, INC.
发明人： MELANSON, John, L. , SINGH, Rahul , DRAKSHAPALLI, Prashanth , BRUMMEL, Dale , HODAPP, Stephen, T.
IPC分类号： H03D3/14
CPC分类号： H03M3/424 , G01V1/181 , H03M1/066 , H03M3/388 , H03M3/454
摘要： A low power analog-to-digital converter configured to sense sensor signals may include a loop filter and a feedback digital-to-analog converter. The loop filter may have a loop filter input configured to receive an input current signal from a sensor and generate an output signal responsive to the input current signal. The feedback digital-to-analog converter may have a feedback output configured to generate a current-mode or charge-mode feedback output signal responsive to the output signal, the feedback output coupled to the loop filter input in order to combine the input current signal and the feedback output signal at the input.
摘要翻译：被配置为感测传感器信号的低功率模数转换器可以包括环路滤波器和反馈数模转换器。环路滤波器可以具有环路滤波器输入，其被配置为从传感器接收输入电流信号并且响应于输入电流信号而生成输出信号。反馈数模转换器可以具有被配置为响应于输出信号生成电流模式或电荷模式反馈输出信号的反馈输出，反馈输出耦合到环路滤波器输入以便组合输入电流信号和输入端的反馈输出信号。

68. 发明申请

WO2015017315A1 COMPENSATING FOR A REVERSE RECOVERY TIME PERIOD OF A BIPOLAR JUNCTION TRANSISTOR (BJT) IN SWITCH-MODE OPERATION OF A LIGHT-EMITTING DIODE (LED)-BASED BULB 审中-公开
标题翻译：双极性晶体管（BJT）在发光二极管（LED）的开关模式操作中的反向恢复时间的补偿
公开(公告)号：WO2015017315A1
公开(公告)日：2015-02-05
申请号：PCT/US2014/048388
申请日：2014-07-28
申请人： CIRRUS LOGIC, INC.
发明人： MELANSON, John, L. , RENGACHARI, Thirumalai , MARU, Siddharth , ZANBAGHI, Ramin , SINGH, Rahul , AZRAI, Firas
IPC分类号： G05F1/10
CPC分类号： H05B33/0815 , H02M3/156 , H05B33/0845 , H05B37/02
摘要： A turn-off transition time period, also referred to as a reverse recovery time period, may be compensated for by a controller of a power stage including a bipolar junction transistor (BJT). The reverse recovery time period may be measured in one switching cycle and a subsequent switching cycle may include compensations based on the measured reverse recovery time period. That is the switching on and off of the BJT may be compensated to obtain a desired average output current to a load. When the reverse recovery time period is known, an error in the peak current obtained due to the reverse recovery time period may be calculated. The calculated error may be used to offset the target peak current for controlling the switching of the BJT to begin a turn-off transition of the BJT earlier in a switching cycle and thus reduce error in peak current at the BJT.
摘要翻译：还可以通过包括双极结型晶体管（BJT）的功率级的控制器补偿关断转换时间段（也称为反向恢复时间周期）。可以在一个开关周期内测量反向恢复时间段，并且随后的开关周期可以包括基于所测量的反向恢复时间段的补偿。也就是说，可以补偿BJT的接通和断开以获得期望的负载平均输出电流。当已知反向恢复时间周期时，可以计算由于反向恢复时间段而获得的峰值电流的误差。计算出的误差可用于偏移目标峰值电流，以控制BJT的开关，以便在开关周期中较早地开始BJT的关断转换，从而减小BJT的峰值电流误差。

69. 发明申请

WO2013003673A1 TRANSFORMER-ISOLATED LED LIGHTING CIRCUIT WITH SECONDARY-SIDE DIMMING CONTROL 审中-公开
标题翻译：具有二次侧调节控制的变压器隔离式LED照明电路
公开(公告)号：WO2013003673A1
公开(公告)日：2013-01-03
申请号：PCT/US2012/044815
申请日：2012-06-29
申请人： CIRRUS LOGIC, INC.
发明人： MELANSON, John, L. , KING, Eric
IPC分类号： H02M1/36 , H05B33/08
CPC分类号： H05B33/0815 , H05B33/0845 , Y02B20/345 , Y02B20/347
摘要： A transformer isolated LED lighting circuit supplies current from a secondary-side storage capacitor to one or more LED strings in conformity with one or more dimming values. The dimming values are communicated through the transformer by patterns or codes provided in pulses of a power converter circuit that charges the storage capacitor from the primary side of the transformer, or alternatively by a special modulated signal provided in addition to the switching pulses.
摘要翻译：变压器隔离的LED照明电路将电流从次级侧存储电容器提供给符合一个或多个调光值的一个或多个LED串。调光值通过变压器通过在从变压器的初级侧对存储电容器充电的功率转换器电路的脉冲中提供的模式或代码，或者通过除开关脉冲之外提供的特殊调制信号来传送。

70. 发明申请

WO2012061454A2 DUTY FACTOR PROBING OF A TRIAC-BASED DIMMER 审中-公开
标题翻译：基于TRIAC的调光器的负载因子探测
公开(公告)号：WO2012061454A2
公开(公告)日：2012-05-10
申请号：PCT/US2011/058884
申请日：2011-11-02
申请人： CIRRUS LOGIC, INC.
发明人： KING, Eric , MELANSON, John, L.
IPC分类号： H02M1/36
CPC分类号： H05B33/0845 , G01R23/02 , H05B33/0815 , Y02B20/346
摘要： A power supply circuit for operating high-efficiency lighting devices from a thyristor- controlled dimmer determines the dimming value, i.e., the duty factor of the output of the dimmer by periodically probing the output of the dimmer. A minimum conductance is applied across the output of the dimmer during probing intervals that begin at the turn-on time of the dimmer and last until enough information has been gathered to correctly predict a next zero crossing of the AC line voltage that supplies the input of the dimmer. The dimming value is determined from the time interval between the predicted zero-crossing and a next turn-on time of the dimmer. The probing can be performed at intervals of an odd number of half-cycles of the AC line frequency so that a DC offset is not introduced within internal timing circuits of the dimmer. The AC line frequency can also be determined from a time interval between the predicted zero crossings.
摘要翻译：用于从可控硅控制的调光器操作高效率照明装置的电源电路通过周期性地探测调光器的输出来确定调光值，即调光器输出的占空因数。在从调光器的接通时间开始的探测间隔期间，在调光器的输出端施加最小电导，直到足够的信息被收集以正确地预测提供输入的AC线电压的下一个过零点调光器调光值由调光器的预测过零点和下一个导通时间之间的时间间隔确定。可以以交流线路频率的奇数个半周期的间隔执行探测，使得在调光器的内部定时电路内不引入DC偏移。 AC线频率也可以从预测的零交叉之间的时间间隔确定。

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