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61. 发明申请

US20070063277A1 MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT 审中-公开
标题翻译：在单闸门上多个低K和高K门氧化物用于较低的电容和改进的驱动电流
公开(公告)号：US20070063277A1
公开(公告)日：2007-03-22
申请号：US11162778
申请日：2005-09-22
申请人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
发明人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/512 , H01L21/26586 , H01L21/31155 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, with the proviso that when the first gate oxide is high k, than the second gate oxide is low k, or when the first gate oxide is low k, than the second gate oxide is high k.
摘要翻译：本发明提供一种具有至少一个CMOS器件的半导体结构，其中米勒电容（即，重叠电容）被减小并且驱动电流得到改善。本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，条件是当第一栅极氧化物高于第二栅极氧化物为低k，或者当第一栅极氧化物为低k时，第二栅极氧化物为高k。

62. 发明申请

US20060154428A1 INCREASING DOPING OF WELL COMPENSATING DOPANT REGION ACCORDING TO INCREASING GATE LENGTH 审中-公开
标题翻译：增加ELL TING D ANT ANT ANT。。。。。
公开(公告)号：US20060154428A1
公开(公告)日：2006-07-13
申请号：US10905591
申请日：2005-01-12
申请人： Omer Dokumaci
发明人： Omer Dokumaci
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/268 , H01L29/66537 , H01L29/66545
摘要： Methods and resulting structure of implementing a compensating implant that creates more compensation doping as the gate length is increased are disclosed. In particular, the invention performs an angled compensation implant through a gate opening during the damascene process such that the compensating dopant concentration increases as the gate length increases. In this fashion, the threshold voltage of a longer device is reduced much more than the threshold voltage of a shorter device, thereby reducing the threshold voltage of the longer device to acceptable levels without affecting the threshold voltage of the shorter device. The invention is especially advantageous relative to super-steep retrograde wells.
摘要翻译：公开了实现在栅极长度增加时产生更多补偿掺杂的补偿注入的方法和结果。特别地，本发明在镶嵌工艺期间通过栅极开口执行倾斜的补偿注入，使得补偿掺杂剂浓度随着栅极长度的增加而增加。以这种方式，较长器件的阈值电压比较短器件的阈值电压低得多，从而将较长器件的阈值电压降低到可接受的电平，而不影响较短器件的阈值电压。本发明相对于超陡逆行井特别有利。

63. 发明授权

US07060539B2 Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby 失效
标题翻译：具有T形翅片的FinFET器件的制造方法和由此制造的器件
公开(公告)号：US07060539B2
公开(公告)日：2006-06-13
申请号：US10790550
申请日：2004-03-01
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L21/335 , H01L21/8232
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/7842
摘要： An FET device with a source island and a drain island is formed on a horizontal surface of a substrate comprising an insulating material. A channel structure formed over the horizontal surface of the substrate, which connects between the drain and the source, comprises a planar semiconductor channel fin formed above a vertical fin. The planar and vertical fins form a T-shaped cross-section. The bottom of the vertical fin contacts the horizontal surface of the substrate and the planar fin contacts the top of the vertical fin. A gate dielectric layer covers exposed surfaces of the channel structure. A gate electrode straddles the channel gate dielectric and the channel structure. A sacrificial layer, e.g. SiGe, deposited upon the substrate before forming the vertical fin, may be a semiconductor or dielectric material. The planar fin comprises a semiconductor material such as Si, SiGe or Ge.
摘要翻译：具有源极岛和漏极岛的FET器件形成在包括绝缘材料的衬底的水平表面上。在衬底的水平表面上形成的沟道结构，其连接在漏极和源极之间，包括形成在垂直鳍上方的平面半导体沟道鳍。平面和垂直翅片形成T形横截面。垂直翅片的底部接触衬底的水平表面，并且平面翅片接触垂直翅片的顶部。栅介质层覆盖通道结构的暴露表面。栅电极横跨沟道栅极电介质和沟道结构。牺牲层，例如在形成垂直翅片之前沉积在衬底上的SiGe可以是半导体或电介质材料。平面翅片包括诸如Si，SiGe或Ge的半导体材料。

64. 发明申请

US20060076627A1 ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION 有权
标题翻译：通过外延界面有限扩散形成的超声结构
公开(公告)号：US20060076627A1
公开(公告)日：2006-04-13
申请号：US10711899
申请日：2004-10-12
申请人： Huajie Chen , Omer Dokumaci , Oleg Gluschenkov , Werner Rausch
发明人： Huajie Chen , Omer Dokumaci , Oleg Gluschenkov , Werner Rausch
IPC分类号： H01L29/94
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
摘要翻译：形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。更具体地，本发明增加了硅衬底的顶表面的氧含量。优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。这允许本发明在硅衬底的顶表面上外延生长硅层。此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

65. 发明申请

US20060073649A1 Method for reduced N+ diffusion in strained Si on SiGe substrate 失效
标题翻译： SiGe衬底上应变Si中N +扩散减少的方法
公开(公告)号：US20060073649A1
公开(公告)日：2006-04-06
申请号：US11283882
申请日：2005-11-22
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/26513 , H01L29/1054 , H01L29/6656
摘要： Method for manufacturing a semiconductor device. The method includes forming source and drain extension regions in an upper surface of a SiGe-based substrate. The source and drain extension regions contain an N type impurity. Reducing vacancy concentration in the source and drain extension regions to decrease diffusion of the N type impurity contained in the first source and drain extension regions.
摘要翻译：半导体器件的制造方法该方法包括在基于SiGe的衬底的上表面中形成源极和漏极延伸区域。源极和漏极延伸区域包含N型杂质。降低源极和漏极延伸区域中的空位浓度，以减少第一源极和漏极延伸区域中包含的N型杂质的扩散。

66. 发明申请

US20050258515A1 Embedded stressed nitride liners for CMOS performance improvement 有权
标题翻译：嵌入式应力氮化物衬垫可提高CMOS性能
公开(公告)号：US20050258515A1
公开(公告)日：2005-11-24
申请号：US10851828
申请日：2004-05-21
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L21/302 , H01L21/336 , H01L21/8238 , H01L23/58
CPC分类号： H01L21/823807 , H01L21/28247 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.
摘要翻译：本发明提供了一种半导体器件，其包括位于衬底的台面部分上的栅极区域; 以及位于所述栅极区域上的氮化物衬垫和与所述栅极区域相邻的所述衬底的凹陷表面，所述氮化物衬垫向所述栅极区域下方的器件沟道施加压力。在器件通道上产生的应力是大约275MPa至大约450MPa的纵向应力。

67. 发明申请

US20050104131A1 Silicon device on Si:C-OI and SGOI and method of manufacture 有权
标题翻译： Si：C-OI和SGOI上的硅器件及其制造方法
公开(公告)号：US20050104131A1
公开(公告)日：2005-05-19
申请号：US10715400
申请日：2003-11-19
申请人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
发明人： Dureseti Chidambarrao , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： H01L21/82 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/24 , H01L29/808 , H01L29/10 , H01L27/01 , H01L29/00 , H01L31/036
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。在第一岛和第二岛上形成不同材料的层。科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

68. 发明申请

US20050082616A1 High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture 有权
标题翻译：使用Si：C和SiGe外延源/漏极的高性能应力增强型MOSFET及其制造方法
公开(公告)号：US20050082616A1
公开(公告)日：2005-04-21
申请号：US10689506
申请日：2003-10-20
申请人： Huajie Chen , Dureseti Chidambarrao , Omer Dokumaci
发明人： Huajie Chen , Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L20060101 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/10
CPC分类号： H01L29/7848 , H01L21/3081 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.
摘要翻译：半导体器件及半导体器件的制造方法。半导体器件包括用于pFET和nFET的沟道。在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

69. 发明申请

US20050064687A1 SILICIDE PROXIMITY STRUCTURES FOR CMOS DEVICE PERFORMANCE IMPROVEMENTS 失效
标题翻译：用于CMOS器件性能改进的硅化物接近结构
公开(公告)号：US20050064687A1
公开(公告)日：2005-03-24
申请号：US10605310
申请日：2003-09-22
申请人： Dureseti Chidambarrao , Omer Dokumaci , Rajesh Rengarajan , An Steegen
发明人： Dureseti Chidambarrao , Omer Dokumaci , Rajesh Rengarajan , An Steegen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/38 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/458 , H01L29/7842 , H01L29/7845 , H01L29/78654
摘要： A method for manufacturing an integrated circuit having a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor on a semiconductor wafer by creating a spacer having a first width for the n-type field effect transistor and creating a spacer having a second width for the p-type field effect transistor, the first width being greater than the second width and depositing silicide material on the semiconductor wafer such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor and compressive stresses are formed within a channel of the p-type field effect transistor.
摘要翻译：一种制造集成电路的方法，该集成电路具有在半导体晶片上具有n型场效应晶体管和p型场效应晶体管的多个半导体器件，该半导体器件具有用于n型场效应晶体管的具有第一宽度的间隔物，以及产生具有用于p型场效应晶体管的第二宽度的间隔物，第一宽度大于第二宽度，并且在半导体晶片上沉积硅化物材料，使得在n型场效应的沟道内形成拉伸机械应力在p型场效应晶体管的沟道内形成晶体管和压应力。

70. 发明申请

US20050051851A1 STRUCTURE AND METHOD OF MAKING STRAINED CHANNEL CMOS TRANSISTORS HAVING LATTICE-MISMATCHED EPITAXIAL EXTENSION AND SOURCE AND DRAIN REGIONS 有权
标题翻译：具有狭缝分离的外延延伸和源和漏区的应变通道CMOS晶体管的结构和方法
公开(公告)号：US20050051851A1
公开(公告)日：2005-03-10
申请号：US10605134
申请日：2003-09-10
申请人： Huajie Chen , Dureseti Chidambarrao , Omer Dokumaci , Haining Yang
发明人： Huajie Chen , Dureseti Chidambarrao , Omer Dokumaci , Haining Yang
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6653 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7848
摘要： A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.
摘要翻译：提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。应力由第一半导体晶格失配的第二半导体层施加。第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。

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