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61. 发明授权

US5638326A Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device 失效
标题翻译：使用闪存设备中的参考单元的信号，并行页缓冲区验证或读取字线上的单元格
公开(公告)号：US5638326A
公开(公告)日：1997-06-10
申请号：US630919
申请日：1996-04-05
申请人： Shane C. Hollmer , Pau-Ling Chen , Binh Q. Le
发明人： Shane C. Hollmer , Pau-Ling Chen , Binh Q. Le
IPC分类号： G11C7/14 , G11C16/28 , G11C7/00
CPC分类号： G11C7/14 , G11C16/28
摘要： A flash memory including a page buffer with bias circuitry and a reference array enabling reading and verifying values stored on a word line of memory cells in parallel using the page buffer irrespective of temperature, Vcc, and process variations. The bias circuitry includes a cascode transistor having a source connected to the reference cell array which provides a single reference signal. The bias cascode couples the reference signal to an input of a bias inverter in the bias generator, while a bias load transistor in the bias generator couples Vcc to the bias inverter input. The page buffer includes a set of latches that are each coupled to a memory cell by a cascode. A first inverter in each latch has transistors with sizes matching the transistors in the bias inverter. A latch load transistor is connected between a pull-up and pull-down transistor of a second inverter in each latch and is sized to match the bias load transistor. Gates of the bias load transistor and the latch load transistor are both coupled to the output of the bias inverter enabling the first inverter of each latch to have an input mirroring the input of the bias inverter.
摘要翻译：包括具有偏置电路的页缓冲器和参考阵列的闪速存储器，其能够使用页缓冲器并行读取和验证存储单元的字线上的值，而与温度，Vcc和工艺变化无关。偏置电路包括具有连接到参考单元阵列的源的共源共栅晶体管，其提供单个参考信号。偏置共源共栅将参考信号耦合到偏置发生器中的偏置反相器的输入，而偏置发生器中的偏置负载晶体管将Vcc耦合到偏置反相器输入。页面缓冲器包括一组锁存器，每个锁存器通过级联耦合到存储器单元。每个锁存器中的第一个反相器具有与偏置反相器中的晶体管尺寸匹配的晶体管。锁存器负载晶体管连接在每个锁存器中的第二反相器的上拉和下拉晶体管之间，并且其大小适于匹配偏置负载晶体管。偏置负载晶体管和锁存负载晶体管的栅极都耦合到偏置反相器的输出，使得每个锁存器的第一反相器具有镜像偏置反相器的输入的输入。

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