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61. 发明授权

US08614499B2 Memory cell having heater material and variable resistance material embedded within insulating material 有权
标题翻译：具有加热器材料和可变电阻材料的存储单元嵌入绝缘材料中
公开(公告)号：US08614499B2
公开(公告)日：2013-12-24
申请号：US13486678
申请日：2012-06-01
申请人： John Smythe
发明人： John Smythe
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.
摘要翻译：一种可变电阻存储单元结构及其形成方法。该方法包括形成第一电极，在第一电极上形成绝缘材料，在绝缘材料中形成通孔以暴露第一电极的表面，在气体簇离子束中形成通孔内的加热材料，形成可变电阻并且形成第二电极，使得加热材料和可变电阻材料设置在第一和第二电极之间。

62. 发明申请

US20130014696A1 APPARATUS TO CONDUCT SPIN-ON FILM PROCESSING 审中-公开
标题翻译：设计旋转电影处理
公开(公告)号：US20130014696A1
公开(公告)日：2013-01-17
申请号：US13619275
申请日：2012-09-14
申请人： Nishant Sinha , Gurtej S. Sandhu , John Smythe
发明人： Nishant Sinha , Gurtej S. Sandhu , John Smythe
IPC分类号： B05C9/00 , B05C13/00
CPC分类号： H01L21/02282 , B01D19/0078 , B01F11/0071 , B05C11/02 , B05D1/005 , B05D3/12 , B08B3/12 , G03D3/04 , G03F7/162 , H01L21/31051 , H01L21/31058 , H01L21/312 , H01L21/67017 , H01L21/67092 , H01L21/6715 , H01L21/76819
摘要： An apparatus and process operate to impose acoustic radiation pressure upon a spin-on mass to alter topography of the spin-on mass. Other apparatus and processes are disclosed.
摘要翻译：一种装置和方法用于对旋转质量施加声辐射压力以改变旋转质量的形貌。公开了其他装置和方法。

63. 发明申请

US20120146222A1 Circuit Structures and Electronic Systems 有权
标题翻译：电路结构与电子系统
公开(公告)号：US20120146222A1
公开(公告)日：2012-06-14
申请号：US13401534
申请日：2012-02-21
申请人： John Smythe
发明人： John Smythe
IPC分类号： H01L23/482
CPC分类号： H01L21/02126 , H01L21/02211 , H01L21/02222 , H01L21/288 , H01L21/316 , H01L21/32051 , H01L21/76831 , H01L21/76843 , H01L21/76877
摘要： The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
摘要翻译：本发明包括在与半导体衬底相关联的波状表面形貌上保形地形成层的方法。起伏的表面形貌可以首先暴露于氧化钛，氧化钕，氧化钇，氧化锆和氧化钒中的一种或多种以处理表面，并且随后可以暴露于沿着被处理的表面共形形成层的材料。该材料可以例如包括铝硅烷和铝硅氮烷中的一种或两种。本发明还包括在包含氧化钛，氧化钇，氧化锆和氧化钒中的一种或多种的衬垫上形成保形层的半导体结构。

64. 发明申请

US20110182103A1 GCIB-TREATED RESISTIVE DEVICE 有权
标题翻译： GCIB处理电阻器件
公开(公告)号：US20110182103A1
公开(公告)日：2011-07-28
申请号：US12693936
申请日：2010-01-26
申请人： John Smythe , Gurtej S. Sandhu
发明人： John Smythe , Gurtej S. Sandhu
IPC分类号： G11C11/56 , H01L21/34 , H01L45/00
CPC分类号： H01L45/165 , G11C13/0007 , G11C2213/56 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1641 , H01L45/1683
摘要： The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.
摘要翻译：本公开包括GCIB处理的电阻性装置，利用GCIB处理的电阻性装置（例如，作为开关，存储器单元）的装置以及用于形成经GCIB处理的电阻装置的方法。形成GCIB处理的电阻性器件的一种方法包括形成下电极，并在下电极上形成氧化物材料。将氧化物材料暴露于气体簇离子束（GCIB），直到氧化物材料的第一部分的电阻相对于氧化物材料的第二部分的电阻发生变化。上电极形成在第一部分上。

65. 发明授权

US07902084B2 Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors 有权
标题翻译：至少使用臭氧和TEOS作为沉积前体的二氧化硅沉积方法
公开(公告)号：US07902084B2
公开(公告)日：2011-03-08
申请号：US11773622
申请日：2007-07-05
申请人： John Smythe , Gurtej S. Sandhu
发明人： John Smythe , Gurtej S. Sandhu
IPC分类号： H01L21/31
CPC分类号： H01L21/31612 , H01L21/02164 , H01L21/02304 , H01L21/02312 , H01L21/02315 , H01L21/3105
摘要： Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated.
摘要翻译：本文公开的实施方案涉及至少使用臭氧和原硅酸四乙酯（TEOS）作为沉积前体的二氧化硅沉积方法。在一个实施方案中，使用至少臭氧和TEOS作为沉积前体的二氧化硅沉积方法包括在低于大气压的压力条件下将包含臭氧和TEOS的前体流入基底，以有效地将具有外表面的含二氧化硅的材料沉积到基底上。与所述处理之前的外表面上的任何羟基存在相比，外表面被有效地对从外表面添加羟基或除去羟基之一进行处理。在处理之后，包含臭氧和TEOS的前体在有效将含二氧化硅的材料沉积到经处理的基底的外表面上的低于大气压的压力条件下流到基底。预期其他实施例。

66. 发明申请

US20100288994A1 METHOD OF FORMING MEMORY CELL USING GAS CLUSTER ION BEAMS 有权
公开(公告)号：US20100288994A1
公开(公告)日：2010-11-18
申请号：US12844541
申请日：2010-07-27
申请人： John Smythe
发明人： John Smythe
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.

67. 发明申请

US20100221920A1 SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES 有权
标题翻译：用于触点接触和相关结构的间隔工艺
公开(公告)号：US20100221920A1
公开(公告)日：2010-09-02
申请号：US12781681
申请日：2010-05-17
申请人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
发明人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
IPC分类号： H01L21/311
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。还公开了与该方法相关联的结构。在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。互连可以由间距倍增形成。为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。可选择定义的材料中的特征被修剪到期望的尺寸。间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。去除可选择定义的材料以留下由间隔物材料限定的掩模。由间隔物材料限定的图案可以转移到基底上，以形成间距接触。在一些实施例中，上电触点可用于电接触衬底中的导电互连。

68. 发明申请

US20100193897A1 SEMICONDUCTOR MATERIAL MANUFACTURE 有权
标题翻译：半导体材料制造
公开(公告)号：US20100193897A1
公开(公告)日：2010-08-05
申请号：US12365734
申请日：2009-02-04
申请人： Nishant Sinha , Gurtej S. Sandhu , John Smythe
发明人： Nishant Sinha , Gurtej S. Sandhu , John Smythe
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L21/76254
摘要： Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.
摘要翻译：电子设备，系统和方法包括结合到晶片或基板的主体区域的半导体层，其中半导体层可以使用电磁辐射结合到主体区域。公开了附加装置，系统和方法。

69. 发明申请

US20090239389A1 Method of Forming a Layer of Material Using an Atomic Layer Deposition Process 审中-公开
标题翻译：使用原子层沉积工艺形成材料层的方法
公开(公告)号：US20090239389A1
公开(公告)日：2009-09-24
申请号：US12476059
申请日：2009-06-01
申请人： Neal Rueger , John Smythe
发明人： Neal Rueger , John Smythe
IPC分类号： H01L21/316 , H01L21/3205
CPC分类号： C23C16/45525 , C23C16/45536
摘要： Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative embodiment, the method includes identifying a target characteristic for the layer of material, determining a precursor pulse time for introducing a precursor gas into the process chamber during the ALD process to produce the target characteristic in the layer of material, and performing the ALD process that comprises a plurality of steps wherein the precursor gas is introduced into the chamber for the determined precursor pulse time to thereby form the layer of material.
摘要翻译：公开了一种在处理工具的处理室中使用原子层沉积（ALD）工艺形成材料层的方法。在一个说明性实施例中，该方法包括识别材料层的目标特性，确定用于在ALD过程期间将前体气体引入处理室的前体脉冲时间，以在材料层中产生目标特性，并执行 ALD方法，其包括多个步骤，其中将前体气体引入到室中用于所确定的前体脉冲时间，从而形成材料层。

70. 发明授权

US07439157B2 Isolation trenches for memory devices 有权
标题翻译：存储器件的隔离沟槽
公开(公告)号：US07439157B2
公开(公告)日：2008-10-21
申请号：US11129884
申请日：2005-05-16
申请人： Zailong Bian , John Smythe , Janos Fucsko , Michael Violette
发明人： Zailong Bian , John Smythe , Janos Fucsko , Michael Violette
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L27/11517
摘要： A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.
摘要翻译：一种方法包括去除衬底的一部分以限定隔离沟槽; 在所述沟槽中的所述衬底的暴露表面上形成第一电介质层; 在至少所述第一介电层上形成第二电介质层，所述第二电介质层含有与所述第一电介质层不同的电介质材料; 沉积第三介电层以填充沟槽; 从沟槽移除第三电介质层的上部并留下覆盖第二介电层的一部分的下部; 在除去上部之后氧化第三电介质层的下部; 从所述沟槽去除所述第二电介质层的暴露部分，从而暴露所述第一介电层的一部分; 以及在所述沟槽中形成覆盖所述第一介电层的暴露部分的第四电介质层。

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