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61. 发明授权

US07056773B2 Backgated FinFET having different oxide thicknesses 失效
公开(公告)号：US07056773B2
公开(公告)日：2006-06-06
申请号：US10709323
申请日：2004-04-28
申请人： Andres Bryant , Omer H. Dokumaci , Hussein I. Hanafi , Edward J. Nowak
发明人： Andres Bryant , Omer H. Dokumaci , Hussein I. Hanafi , Edward J. Nowak
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L29/785 , H01L29/42368 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.

62. 发明授权

US06646305B2 Grounded body SOI SRAM cell 有权
标题翻译：接地体SOI SRAM单元
公开(公告)号：US06646305B2
公开(公告)日：2003-11-11
申请号：US09915061
申请日：2001-07-25
申请人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
发明人： Fariborz Assaderaghi , Andres Bryant , Peter E. Cottrell , Robert J. Gauthier, Jr. , Randy W. Mann , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L27/1104
摘要： A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a source region and a drain region, wherein the bodies of two of the NFETs are electrically connected to ground. Additionally, the bodies of the two PFETs are electrically connected to VDD.
摘要翻译：一种半导体存储器件，包括：在衬底绝缘体的顶部上具有薄硅层的SOI衬底; 以及包括四个NFET和位于薄硅层中的两个PFET的SRAM，每个NFET和PFET具有在源极区域和漏极区域之间的主体区域，其中两个NFET的主体电连接到地。另外，两个PFET的主体电连接到VDD。

63. 发明授权

US06437594B1 SOI pass gate leakage monitor 失效
标题翻译： SOI通孔泄漏监测器
公开(公告)号：US06437594B1
公开(公告)日：2002-08-20
申请号：US09528350
申请日：2000-03-17
申请人： Ronald J. Bolam , Andres Bryant , Edward J. Nowak , Minh H. Tong
发明人： Ronald J. Bolam , Andres Bryant , Edward J. Nowak , Minh H. Tong
IPC分类号： G01R2722
CPC分类号： G01R31/3004
摘要： A monitor for detecting pass gate leakage in a silicon on insulator device and a method for using the same is described herein. A pulse generator supplies a signal to a set of buffers connected in parallel, which pass on a signal to the source side of a series of NFETs. The plurality of NFETs are ordered by increasing channel widths. The NFETs have grounded gates, and therefore will not pass current due to field effects. Each NFET is connected to a latch, and the latches are originally set to the same state. When the signal supplied to the NFET drops from high to low, pass gate leakage will occur through the channel of each NFET. If pass gate leakage through any given NFET is sufficient, the latch will change states. The latch output signal is sent to a shift register, which can be made to output information. By incorporating the monitor on the chip, pass gate leakage tolerances and specifications can be established in-line during manufacture.
摘要翻译：这里描述了一种用于检测绝缘体上硅器件中的漏极泄漏的监视器及其使用方法。脉冲发生器将信号提供给并联连接的一组缓冲器，该缓冲器将信号传递到一系列NFET的源极侧。通过增加通道宽度来排列多个NFET。 NFET具有接地栅极，因此由于场效应而不会通过电流。每个NFET连接到一个锁存器，并且锁存器最初设置为相同的状态。当提供给NFET的信号从高到低时，通过每个NFET的通道将发生栅极泄漏。如果通过任何给定NFET的漏极泄漏就足够了，锁存器将改变状态。锁存器输出信号发送到移位寄存器，可以输出信息。通过将显示器结合在芯片上，可以在制造过程中在线建立传递门泄漏公差和规格。

64. 发明授权

US06200843B1 High-voltage, high performance FETs 失效
标题翻译：高电压，高性能FET
公开(公告)号：US06200843B1
公开(公告)日：2001-03-13
申请号：US09159841
申请日：1998-09-24
申请人： Andres Bryant , Edward J. Nowak , Minh H. Tong
发明人： Andres Bryant , Edward J. Nowak , Minh H. Tong
IPC分类号： H01L218238
CPC分类号： H01L29/42368 , H01L21/28167 , H01L21/28194 , H01L21/823857 , H01L27/092 , Y10S438/981
摘要： A method for forming a semiconductor device. A substrate is provided. A first electrically insulating layer is formed on the substrate. A second electrically insulating layer is formed on the first electrically insulating layer. Openings are formed through the second electrically insulating layer down to the level of the first electrically insulating layer. Spacers are formed on opposing sidewalls of the openings. The spacers on one of the opposing side walls of the openings are removed, thereby exposing portions of the first electrically insulating layer. Exposed portions of the first electrically insulating layer in the openings are removed, thereby exposing portions of the substrate. The spacers on another of the opposing sidewalls of the openings are removed, thereby exposing portions of the first electrically insulating layer. A third electrically insulating layer is formed in the openings over the exposed portions of the first electrically insulating layer and the exposed portions of the substrate.
摘要翻译：一种形成半导体器件的方法。提供基板。在基板上形成第一电绝缘层。在第一电绝缘层上形成第二电绝缘层。通过第二电绝缘层形成通向第一电绝缘层的水平面的开口。间隔件形成在开口的相对侧壁上。去除开口的一个相对侧壁上的间隔件，从而暴露第一电绝缘层的部分。去除开口中的第一电绝缘层的暴露部分，从而暴露基板的部分。去除开口的另一相对侧壁上的间隔物，从而暴露第一电绝缘层的部分。在第一电绝缘层的暴露部分和基板的暴露部分的开口中形成第三电绝缘层。

65. 发明授权

US09064974B2 Barrier trench structure and methods of manufacture 有权
标题翻译：阻隔沟槽结构和制造方法
公开(公告)号：US09064974B2
公开(公告)日：2015-06-23
申请号：US13108144
申请日：2011-05-16
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/092 , H01L21/84 , H01L21/762 , H01L27/12 , H01L21/8234
CPC分类号： H01L27/092 , H01L21/76283 , H01L21/823481 , H01L21/84 , H01L27/1203 , H01L29/0642
摘要： A method includes forming at least one shallow trench isolation structure in a substrate to isolate adjacent different type devices. The method further includes forming a barrier trench structure in the substrate to isolate diffusions of adjacent same type devices. The method further includes spanning the barrier trench structure with material to connect the diffusions of the adjacent same type device, on a same level as the adjacent same type devices.
摘要翻译：一种方法包括在衬底中形成至少一个浅沟槽隔离结构以隔离相邻的不同类型的器件。该方法还包括在衬底中形成阻挡沟槽结构以隔离相邻相同类型器件的扩散。该方法进一步包括将阻挡沟槽结构与材料连接，以将相邻相同类型器件的扩散连接在与相邻相同类型器件相同的水平上。

66. 发明申请

US20130154003A1 ASYMMETRIC ANTI-HALO FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：不对称抗HALO场效应晶体管
公开(公告)号：US20130154003A1
公开(公告)日：2013-06-20
申请号：US13329440
申请日：2011-12-19
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/66492 , H01L29/66583 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A method of forming an integrated circuit structure implants a first compensating implant into a substrate. The method patterns a mask on the first compensating implant in the substrate. The mask includes an opening exposing a channel location of the substrate. The method implants a second compensating implant into the channel location of the substrate. The second compensating implant is made through the opening in the mask and at an angle that is offset from perpendicular to the top surface of the substrate. The second compensating implant is positioned closer to a first side of the channel location relative to an opposite second side of the channel location and the second compensating implant comprises a material having the same doping polarity as the semiconductor channel implant. Then, the method forms a gate conductor above the channel location of the substrate in the opening of the mask.
摘要翻译：形成集成电路结构的方法将第一补偿植入物植入衬底。该方法在衬底中的第一补偿植入物上形成掩模。掩模包括暴露基板的通道位置的开口。该方法将第二补偿植入物植入衬底的通道位置。第二补偿植入物通过掩模中的开口并以与衬底的顶表面垂直的角度形成。第二补偿植入件相对于沟道位置的相对的第二侧被定位成更靠近通道位置的第一侧，并且第二补偿植入物包括具有与半导体沟道植入物相同的掺杂极性的材料。然后，该方法在掩模的开口中在衬底的通道位置之上形成栅极导体。

67. 发明授权

US08217456B1 Low capacitance hi-K dual work function metal gate body-contacted field effect transistor 有权
标题翻译：低电容hi-K双功能金属门体接触场效应晶体管
公开(公告)号：US08217456B1
公开(公告)日：2012-07-10
申请号：US13046084
申请日：2011-03-11
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/778
CPC分类号： H01L29/78615 , H01L29/42384
摘要： Disclosed herein is a field effect transistor (FET), device including a FET, and a method of making the same. In embodiments of the disclosure, a semiconductor-on-insulator (SOI) substrate is provided. The SOI substrate includes a body having a first conductivity type formed in the semiconductor layer of the SOI substrate, the body including a first body region connecting a second body region to a third body region; and a source and a drain, each having a second conductivity type, disposed on opposite sides of the first body region. A first gate electrode having a second work function is disposed above the first body region; and a second gate electrode having a first work function disposed above the second and third body regions. A first gate dielectric layer may be disposed vertically between the first body region and the first gate electrode, and a second gate dielectric layer may be disposed vertically between the second and third body regions and the second gate electrode. The first and second gate electrodes have different work functions.
摘要翻译：本文公开了一种场效应晶体管（FET），包括FET的器件及其制造方法。在本公开的实施例中，提供绝缘体上半导体（SOI）衬底。 SOI衬底包括形成在SOI衬底的半导体层中的具有第一导电类型的主体，该主体包括将第二主体区域连接到第三主体区域的第一主体区域; 以及源极和漏极，每个具有第二导电类型，设置在第一体区的相对侧上。具有第二功函数的第一栅电极设置在第一体区的上方; 以及第二栅电极，其具有设置在第二和第三体区之上的第一功函数。第一栅极电介质层可以垂直地设置在第一体区域和第一栅电极之间，并且第二栅极电介质层可以垂直地设置在第二和第三体区域与第二栅电极之间。第一和第二栅电极具有不同的功函数。

68. 发明授权

US07981772B2 Methods of fabricating nanostructures 失效
标题翻译：制造纳米结构的方法
公开(公告)号：US07981772B2
公开(公告)日：2011-07-19
申请号：US12344696
申请日：2008-12-29
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
IPC分类号： H01L21/3213
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0669 , H01L29/0673 , H01L29/16 , H01L29/161 , Y10S977/888
摘要： A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the SiX material. The method further includes etching the SiX material to expose portions of the Si material and etching the exposed portions of the Si material. The method also includes breaking away the Si material to form silicon nanowires.
摘要翻译：示出了制造纳米结构的方法，更具体地说，涉及制造硅纳米线的方法。制造纳米线的方法包括在衬底上形成SiX材料和材料Si的夹层结构，并蚀刻夹层结构以暴露Si材料和SiX材料的侧壁。该方法还包括蚀刻SiX材料以暴露Si材料的部分并蚀刻Si材料的暴露部分。该方法还包括分离Si材料以形成硅纳米线。

69. 发明授权

US07971158B2 Spacer fill structure, method and design structure for reducing device variation 失效
标题翻译：间隔填充结构，减少装置变化的方法和设计结构
公开(公告)号：US07971158B2
公开(公告)日：2011-06-28
申请号：US12144004
申请日：2008-06-23
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.
摘要翻译：提供了用于间隔物填充结构的设计结构，并且更具体地，提供了间隔件填充结构，制造方法和用于减小装置变化的设计结构。该结构包括在器件的不同区域中的多个虚拟填充形状，其被配置为使得栅极周边与栅极面积比将导致芯片上的总周长密度是均匀的。

70. 发明授权

US07943997B2 Fully-depleted low-body doping field effect transistor (FET) with reverse short channel effects (SCE) induced by self-aligned edge back-gate(s) 有权
标题翻译：具有由自对准边缘后栅极引起的反向短沟道效应（SCE）的全耗尽低体积掺杂场效应晶体管（FET）
公开(公告)号：US07943997B2
公开(公告)日：2011-05-17
申请号：US12104683
申请日：2008-04-17
申请人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： James W. Adkisson , Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L29/66621 , H01L29/78645 , H01L29/78648 , H01L29/78696
摘要： Disclosed are embodiments of a field effect transistor (FET) and, more particularly, a fully-depleted, thin-body (FDTB) FET that allows for scaling with minimal short channel effects, such as drain induced barrier lowering (DIBL) and saturation threshold voltage (Vtsat) roll-off, at shorter channel lengths. The FDTB FET embodiments are configured with either an edge back-gate or split back-gate that can be biased in order to selectively adjust the potential barrier between the source/drain regions and the channel region for minimizing off-state leakage current between the drain region and the source region and/or for varying threshold voltage. These unique back-gate structures avoid the need for halo doping to ensure linear threshold voltage (Vtlin) roll-up at smaller channel lengths and, thus, avoid across-chip threshold voltage variations due to random doping fluctuations. Also disclosed are method embodiments for forming such FETs.
摘要翻译：公开了场效应晶体管（FET）的具体实施例，更具体地说，是允许以最小的短沟道效应（例如漏极感应势垒降低（DIBL）和饱和阈值））进行缩放的完全耗尽的薄体（FDTB）FET 电压（Vtsat）滚降，通道长度较短。 FDTB FET实施例配置有可被偏置的边缘背栅极或分支反向栅极，以便选择性地调节源极/漏极区域和沟道区域之间的势垒，以最小化漏极之间的截止状态漏电流区域和源极区域和/或用于改变阈值电压。这些独特的背栅结构避免了对光晕掺杂的需要，以确保较小通道长度的线性阈值电压（Vtlin）汇总，从而避免由于随机掺杂波动引起的跨芯片阈值电压变化。还公开了用于形成这种FET的方法实施例。

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