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61. 发明申请

US20050227415A1 Method for fabricating encapsulated semiconductor components 有权
公开(公告)号：US20050227415A1
公开(公告)日：2005-10-13
申请号：US11146397
申请日：2005-06-07
申请人： Warren Farnworth , Alan Wood , Trung Doan
发明人： Warren Farnworth , Alan Wood , Trung Doan
IPC分类号： H01L21/301 , H01L21/304 , H01L21/44 , H01L21/56 , H01L21/60 , H01L21/68 , H01L21/768 , H01L21/78 , H01L23/24 , H01L23/31 , H01L23/367 , H01L23/48 , H01L23/485 , H01L23/49 , H01L23/495 , H01L29/06
CPC分类号： H01L23/48 , B33Y70/00 , B33Y80/00 , H01L21/304 , H01L21/3043 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/76802 , H01L21/76898 , H01L21/78 , H01L23/24 , H01L23/3114 , H01L23/36 , H01L23/3672 , H01L23/481 , H01L23/49531 , H01L23/49575 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/27 , H01L24/94 , H01L24/96 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2221/68327 , H01L2221/68331 , H01L2221/68372 , H01L2224/0401 , H01L2224/05599 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/13009 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2224/16235 , H01L2224/274 , H01L2224/73104 , H01L2224/73253 , H01L2224/94 , H01L2225/06541 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2225/1094 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01041 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/19042 , H01L2924/3512 , H01L2924/00 , H01L2224/29099 , H01L2224/27
摘要： A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.

62. 发明申请

US20050156297A1 Semiconductor package including flex circuit, interconnects and dense array external contacts 审中-公开
标题翻译：半导体封装包括柔性电路，互连和密集阵列外部触点
公开(公告)号：US20050156297A1
公开(公告)日：2005-07-21
申请号：US11040555
申请日：2005-01-21
申请人： Warren Farnworth , Alan Wood , Mike Brooks
发明人： Warren Farnworth , Alan Wood , Mike Brooks
IPC分类号： H01L23/498 , H01L21/44 , H01L23/02 , H01L23/495 , H01L29/40
CPC分类号： H01L23/49827 , H01L23/4985 , H01L24/45 , H01L24/48 , H01L2224/02333 , H01L2224/451 , H01L2224/48091 , H01L2224/4813 , H01L2224/48465 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit. Several different embodiments of interconnects are provided including: bumps on the die contacts, bonded to the flex circuit conductors with a conductive adhesive layer; polymer bumps on the conductors, or die contacts, applied in a semi-cured state and then fully cured; solder bumps on the die contacts and conductors, bonded to one another using a bonding tool; rivet-like bonded connections between the conductors and die contacts, formed using metal bumps and a wire bonding or ball bonding apparatus; single point bonded connections between the conductors and die contacts, formed with a bonding tool; and wire bonds between the conductors and die contacts.
摘要翻译：提供了一种芯片级半导体封装和一种制造该封装的方法。该封装包括半导体管芯和连接到管芯的表面的柔性电路。柔性电路包括具有密集阵列的外部触点的聚合物基板和与外部触点电连通的导体图案。封装还包括被配置为在管芯触头（例如，焊盘）之间提供分开的电路径的互连件以及柔性电路上的导体。提供了互连的几个不同实施例，包括：在裸片上的凸起接触，用导电粘合剂层结合到柔性电路导体上; 导体上的聚合物凸块或模具接触件以半固化状态施加，然后完全固化; 使用焊接工具彼此接合的管芯触点和导体上的焊料凸块; 使用金属凸块和引线接合或球焊接装置形成的导体和裸片接触之间的铆钉状接合连接; 导体和裸片接点之间的单点接合连接，用接合工具形成; 以及导体和裸片接触之间的引线键合。

63. 发明授权

US06763578B2 Method and apparatus for manufacturing known good semiconductor die 失效
标题翻译：用于制造已知的良好半导体管芯的方法和装置
公开(公告)号：US06763578B2
公开(公告)日：2004-07-20
申请号：US08975549
申请日：1997-11-20
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： H05K330
CPC分类号： G01R31/2863 , G01R1/0466 , G01R1/0483 , G01R3/00 , G01R31/2831 , G01R31/2867 , H01L21/6835 , H01L22/20 , H01L23/49816 , H01L24/48 , H01L24/85 , H01L2224/16145 , H01L2224/48463 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K3/0058 , H05K3/0067 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/49131 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , Y10T29/49764 , H01L2224/78 , H01L2924/00 , H01L2224/45099
摘要： A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.
摘要翻译：提供了一种用于制造已知的良好半导体晶片的方法和装置。该方法包括以下步骤：测试包含在半导体晶片上的骰子的总功能; 锯切晶片以切割模具; 然后通过组装在具有适于建立管芯上的接合焊盘与外部测试电路之间的电连通的互连的载体中来测试管芯。用于载体的互连可以使用不同的接触技术形成，包括：刚性基板上的厚膜接触构件; 硅衬底上的自限制接触构件; 或具有纹理表面的微型块接触构件。在载体的组装期间，芯片和互连件被光学对准并且被放置成与预定的接触力接触。这就建立了互连上的接触构件和管芯的接合垫之间的电连接。在组装的载体中，管芯和互连件通过包括桥夹，压板和弹簧夹的力分配机构偏压在一起。在对模具进行测试之后，拆下载体并且移除被测试的模具。

64. 发明授权

US5796264A Apparatus for manufacturing known good semiconductor dice 失效
标题翻译：用于制造已知的良好半导体晶片的装置
公开(公告)号：US5796264A
公开(公告)日：1998-08-18
申请号：US823468
申请日：1997-03-19
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , G01R31/02
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R1/06761 , G01R3/00 , G01R31/2831 , G01R31/2863 , H01L2224/16145 , H01L2224/48091 , H01L2224/48463 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01025 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01056 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/30105 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423 , Y10T29/4913 , Y10T29/49144
摘要： A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.
摘要翻译：提供了一种用于制造已知的良好半导体晶片的方法和装置。该方法包括以下步骤：测试包含在半导体晶片上的骰子的总功能; 锯切晶片以切割模具; 然后通过组装在具有适于建立管芯上的接合焊盘与外部测试电路之间的电连通的互连的载体中来测试管芯。用于载体的互连可以使用不同的接触技术形成，包括：刚性基板上的厚膜接触构件; 硅衬底上的自限制接触构件; 或具有纹理表面的微型块接触构件。在载体的组装期间，芯片和互连件被光学对准并且被放置成与预定的接触力接触。这就建立了互连上的接触构件和管芯的接合垫之间的电连接。在组装的载体中，管芯和互连件通过包括桥夹，压板和弹簧夹的力分配机构偏压在一起。在对模具进行测试之后，拆下载体并且移除被测试的模具。

65. 发明授权

US5640762A Method and apparatus for manufacturing known good semiconductor die 失效
公开(公告)号：US5640762A
公开(公告)日：1997-06-24
申请号：US485086
申请日：1995-06-07
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/498 , H01L25/10 , H05K3/00 , H05K3/42 , H05K3/30
CPC分类号： G01R31/2863 , G01R1/0466 , G01R1/0483 , H01L21/6835 , H01L22/20 , H01L23/49816 , H01L24/85 , G01R3/00 , G01R31/2831 , G01R31/2867 , H01L2224/16145 , H01L2224/48463 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423 , Y10T29/49126 , Y10T29/49131 , Y10T29/49144 , Y10T29/49146 , Y10T29/49155 , Y10T29/49764
摘要： A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.

66. 发明授权

US5578526A Method for forming a multi chip module (MCM) 失效
标题翻译：多芯片模块（MCM）的形成方法
公开(公告)号：US5578526A
公开(公告)日：1996-11-26
申请号：US431452
申请日：1995-05-01
申请人： Salman Akram , Warren Farnworth , Alan Wood
发明人： Salman Akram , Warren Farnworth , Alan Wood
IPC分类号： G01R1/04 , G01R31/28 , H01L21/66 , H01L23/13 , H01L23/32 , H01L21/60
CPC分类号： G01R1/04 , G01R31/2863 , H01L22/22 , H01L23/13 , H01L23/32 , H01L2224/16145 , H01L2224/48227 , H01L2924/09701 , H01L2924/10253
摘要： A method for forming a multi chip module for singulated semiconductor dice or dice contained on a wafer is provided. The method includes forming an interconnect adapted to support and establish an electrical connection with the dice. The interconnect includes a substrate formed of a material such as silicon with raised contact members. The raised contact members include projections adapted to penetrate contact locations on the dice (e.g., bond pads) to a limited penetration depth to establish the electrical connection. A conductive layer and conductive traces are formed on the substrate to form an electrical path to the contact members. Programmable links, such as fuses or anti-fuses, can be included in the electrical path for enabling or disabling select dice of the module. A packaged multi chip module assembly can be formed by encapsulation of the dice and substrate in an insulating material or by forming a ceramic base and cover.
摘要翻译：提供一种用于形成包含在晶片上的单片半导体晶片或骰子的多芯片模块的方法。该方法包括形成适于支撑并建立与骰子的电连接的互连。互连包括由诸如具有凸起接触构件的硅的材料形成的衬底。凸起的接触构件包括适于将骰子（例如，接合垫）上的接触位置穿透到有限的穿透深度以建立电连接的突起。导电层和导电迹线形成在衬底上以形成到接触构件的电路径。可编程链路，如保险丝或反熔丝，可以包含在电气路径中，用于启用或禁用模块的选择骰子。封装的多芯片模块组件可以通过将骰子和基板封装在绝缘材料中或通过形成陶瓷基底和盖而形成。

67. 发明申请

US20070088451A1 Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICs will undergo, such as additional repairs 失效
标题翻译：使用有关制造程序集成电路（ICS）的数据的方法已经进行了修复，以选择IC将经历的程序，例如额外修理
公开(公告)号：US20070088451A1
公开(公告)日：2007-04-19
申请号：US11545067
申请日：2006-10-06
申请人： Salman Akram , Warren Farnworth , Derek Gouchnour , David Hembree , Michael Hess , John Jacobson , James Wark , Alan Wood
发明人： Salman Akram , Warren Farnworth , Derek Gouchnour , David Hembree , Michael Hess , John Jacobson , James Wark , Alan Wood
IPC分类号： G06F19/00
CPC分类号： G03F7/7065 , G06F11/006 , H01L2223/5444
摘要： An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the ICs. The ID codes of the ICs are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the ICs is then accessed, and additional repair procedures the ICs may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.
摘要翻译：在集成电路（IC）制造过程中的创造性方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修理，包括将数据与每个的熔丝ID相关联地存储 IC。 IC的ID代码在制造过程中例如在打开/短路测试中自动读取。然后访问与IC的ID代码相关联存储的数据，并且根据所访问的数据选择IC可能经历的附加修复过程。因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。

68. 发明申请

US20070045515A1 Microelectronic imaging devices and associated methods for attaching transmissive elements 有权
公开(公告)号：US20070045515A1
公开(公告)日：2007-03-01
申请号：US11218126
申请日：2005-09-01
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： H01L27/00
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14623 , H01L27/14627 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L31/0232 , H01L2224/13
摘要： Microelectronic imaging devices and associated methods for attaching transmissive elements are disclosed. A manufacturing method in accordance with one embodiment of the invention includes providing an imager workpiece having multiple image sensor dies configured to detect energy over a target frequency. The image sensor dies can include an image sensor and a corresponding lens device positioned proximate to the image sensor. The method can further include positioning standoffs adjacent to the lens devices while the image sensor dies are connected to each other via the imager workpiece. At least one transmissive element can be attached to the workpiece at least proximate to the standoffs so the lens devices are positioned between the corresponding image sensors and the at least one transmissive element. Accordingly, the at least one transmissive element can protect the image sensors while the image sensor dies are still connected. In a subsequent process, the image sensor dies can be separated from each other.

69. 发明申请

US20060275949A1 Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors 有权
标题翻译：具有电路侧触点，导电通孔和背面导体的半导体元件和制造方法
公开(公告)号：US20060275949A1
公开(公告)日：2006-12-07
申请号：US11496180
申请日：2006-07-31
申请人： Warren Farnworth , Alan Wood , Trung Tri Doan
发明人： Warren Farnworth , Alan Wood , Trung Tri Doan
IPC分类号： H01L21/00
CPC分类号： H01L23/48 , B33Y70/00 , B33Y80/00 , H01L21/304 , H01L21/3043 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/76802 , H01L21/76898 , H01L21/78 , H01L23/24 , H01L23/3114 , H01L23/36 , H01L23/3672 , H01L23/481 , H01L23/49531 , H01L23/49575 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/27 , H01L24/94 , H01L24/96 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2221/68327 , H01L2221/68331 , H01L2221/68372 , H01L2224/0401 , H01L2224/05599 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/13009 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2224/16235 , H01L2224/274 , H01L2224/73104 , H01L2224/73253 , H01L2224/94 , H01L2225/06541 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2225/1094 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01041 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/19042 , H01L2924/3512 , H01L2924/00 , H01L2224/29099 , H01L2224/27
摘要： A semiconductor component includes a thinned semiconductor substrate having protective polymer layers on up to six surfaces. The component also includes contacts on a circuit side of the substrate, conductive vias in electrical contact with the contacts, aNd conductors on a backside of the substrate. A method for fabricating the component includes the steps of providing the semiconductor substrate with the contacts on the circuit side, forming conductive vias from the back side in electrical contact with the contacts, and forming conductors on the backside.
摘要翻译：半导体部件包括在多达六个表面上具有保护性聚合物层的变薄的半导体衬底。该部件还包括在基板的电路侧的触点，与触点电接触的导电通孔，在基板的背面上的一个导体。一种制造该部件的方法包括以下步骤：在电路侧提供半导体衬底上的触点，从背面形成与触点电接触的导电通孔，并在背面形成导体。

70. 发明申请

US20060192230A1 Image sensor packages and frame structure thereof 有权
标题翻译：图像传感器封装及其框架结构
公开(公告)号：US20060192230A1
公开(公告)日：2006-08-31
申请号：US11411265
申请日：2006-04-26
申请人： Alan Wood , Kyle Kirby , Warren Farnworth , Salman Akram
发明人： Alan Wood , Kyle Kirby , Warren Farnworth , Salman Akram
IPC分类号： H01L27/148 , H01L31/0203
CPC分类号： H01L27/14618 , B33Y80/00 , H01L27/14625 , H01L2224/48091 , H01L2924/00014
摘要： A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.
摘要翻译：诸如图像传感器封装的半导体封装。框架结构包括每个具有穿过其中的孔的框架阵列，图像传感器与盖玻片，过滤器，透镜或其它部件组合的模具可以精确相互对准地安装在该框架中。单片图像传感器骰子和其他组件可以被拾取并放置在框架结构的每个帧中。或者，框架结构可以被配置为与承载多个图像传感器骰子的晶片对准并且连接到其上，其中沿着框架的周边的任选的向下突出的裙边可以被接收到沿着晶片上的模具位置之间沿着街道切割的切口，然后安装其他包装组件。在任一情况下，将帧结构与单独的图像传感器芯片或连接的晶片组合成单独的图像传感器封装。可以使用各种外部连接方法。

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