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    • 61. 发明申请
    • EQUALIZING PARASITIC CAPACITANCE EFFECTS IN TOUCH SCREENS
    • 在触摸屏中均衡平衡电容效应
    • WO2011127442A3
    • 2011-12-29
    • PCT/US2011031839
    • 2011-04-08
    • APPLE INCCHANG SHIH CHANGHOTELLING STEVEN PORTERYU CHENG HO
    • CHANG SHIH CHANGHOTELLING STEVEN PORTERYU CHENG HO
    • G06F3/041G06F3/044
    • G06F3/044G06F3/0412G06F2203/04111
    • Reduction of the effects of differences in parasitic capacitances in touch screens is provided. A touch screen can include multiple display pixels with stackups that each include a first element and a second element. For example, the first element can be a common electrode, and the second element can be a data line. The display pixels can include a first display pixel including a third element connected to the first element, and the third element can contribute to a first parasitic capacitance between the first and second elements of the first display pixel, for example, by overlapping with the second element. The touch screen can also include a second display pixel lacking the third element. The second display pixel can include a second parasitic capacitance between the first and second elements of the second display pixel. The first and second parasitic capacitances can be substantially equal, for example.
    • 提供了减少触摸屏中寄生电容差异的影响。 触摸屏可以包括具有堆叠的多个显示像素,每个显示像素包括第一元素和第二元素。 例如,第一元件可以是公共电极,第二元件可以是数据线。 显示像素可以包括包括连接到第一元件的第三元件的第一显示像素,并且第三元件可以有助于第一显示像素的第一和第二元素之间的第一寄生电容,例如通过与第二元件重叠 元件。 触摸屏还可以包括缺少第三元素的第二显示像素。 第二显示像素可以包括第二显示像素的第一和第二元素之间的第二寄生电容。 例如,第一和第二寄生电容可以基本上相等。
    • 68. 发明申请
    • VOLTAGE/CURRENT CONTROL APPARATUS AND METHOD
    • 电压/电流控制装置和方法
    • WO2009042419A3
    • 2009-06-11
    • PCT/US2008076075
    • 2008-09-11
    • ALPHA & OMEGA SEMICONDUCTORCHANG YU CHENG
    • CHANG YU CHENG
    • H02M3/335
    • H02M3/1588H02M3/157Y02B70/1466
    • A voltage/current control apparatus and method are disclosed. The apparatus includes a low-side field effect transistor (FET) having a source, a gate and a drain, a high-side field effect transistor (FET) having a source, a gate and a drain, a gate driver integrated circuit (IC), a sample and hold circuit, and a comparator configured to produce a trigger signal at the output when a sum of the first and second input signals is equal to a sum of the third and fourth input signals, wherein the trigger signal is configured to trigger a beginning of a new cycle by turning the gate of the high-side FET "on" and the gate of the low-side FET "off".
    • 公开了一种电压/电流控制装置和方法。 该装置包括具有源极,栅极和漏极的低侧场效应晶体管(FET),具有源极,栅极和漏极的高侧场效应晶体管(FET),栅极驱动器集成电路(IC ),采样和保持电路以及比较器,所述比较器被配置为当所述第一和第二输入信号的和等于所述第三和第四输入信号的和时在所述输出处产生触发信号,其中所述触发信号被配置为 通过将高端FET的栅极“接通”并且将低端FET的栅极“关闭”来触发新周期的开始。