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61. 发明申请

WO2007140120A2 METHODS AND APPARATUS FOR FAST ETHERNET LINK SWITCHOVER IN THE EVENT OF A LINK FAILURE 审中-公开
标题翻译：在链路故障事件中快速以太网链路切换的方法和设备
公开(公告)号：WO2007140120A2
公开(公告)日：2007-12-06
申请号：PCT/US2007/069030
申请日：2007-05-16
申请人： TRANSWITCH CORPORATION , VARADA, Srihari , YEO, Michael, Singngee , MARTY, Diego , SHANLEY, Timothy, M.
发明人： VARADA, Srihari , YEO, Michael, Singngee , MARTY, Diego , SHANLEY, Timothy, M.
IPC分类号： H04J3/14 , H04L12/56
CPC分类号： H04J3/14 , H04J3/085 , H04L49/351 , H04L49/552
摘要： An apparatus for fast failure switch over in an ETHERNET switch includes redundant switch (trunk) ports (a main and a backup) and hardware and software logic for redirecting traffic to the backup port when the main port (or the link associated with it) fails. The switchover is immediate and is based on the content of a local status register which indicates the port (link) status. Thus, frames addressed to the dead port are redirected to the backup port and few frames are lost. The STP function may proceed concurrently and eventually no more frames are addressed to the dead port.
摘要翻译：在以太网交换机中快速故障切换的设备包括冗余交换机（主干和备用）端口以及用于在主端口（或与其相关联的链路）故障时将流量重定向到备份端口的硬件和软件逻辑。切换是立即的，并且基于表示端口（链路）状态的本地状态寄存器的内容。因此，寻址到死端口的帧被重定向到备份端口，并且几帧丢失。 STP功能可以同时进行，最终没有更多的帧被寻址到死端口。

62. 发明申请

WO2007136977A2 METHODS AND APPARATUS FOR TESTING DELAY LOCKED LOOPS AND CLOCK SKEW 审中-公开
标题翻译：用于测试延迟锁定鞋和时钟的方法和装置
公开(公告)号：WO2007136977A2
公开(公告)日：2007-11-29
申请号：PCT/US2007/068014
申请日：2007-05-02
申请人： TRANSWITCH CORPORATION , ABUHAMDEH, Zahi, S. , D'ALESSANDRO, Vincent
发明人： ABUHAMDEH, Zahi, S. , D'ALESSANDRO, Vincent
IPC分类号： G01R23/175
CPC分类号： G06F1/10 , G01R31/31725 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/50012 , H03L7/0812
摘要： According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay introduced by the methods of the invention is preferably adjustable based on the results of a process monitor test. The process monitor test can be run continuously and accounts for process, voltage and temperature. The methods of the invention can also be used to test for clock skew in a clock tree on a chip.
摘要翻译：根据本发明的方法，将另一延迟的DLL信号与参考时钟进行比较，并将延迟的参考时钟信号与DLL信号进行比较。这两个比较在360°信号和180°信号上进行。根据本发明的方法引入的延迟优选地可以基于过程监视测试的结果来调节。过程监控测试可以连续运行，并考虑过程，电压和温度。本发明的方法还可用于测试芯片上的时钟树中的时钟偏移。

63. 发明申请

WO2007024727A2 MULTIPACKET INTERFACE 审中-公开
标题翻译：多路接口
公开(公告)号：WO2007024727A2
公开(公告)日：2007-03-01
申请号：PCT/US2006/032428
申请日：2006-08-21
申请人： TRANSWITCH CORPORATION , MUKHOPADHYAY, Suvhasis , BHATTACHARYA, Santanu , KUMAR, Vikas , SINGH, Kumar, Shakti , DUTTA, Arunava , SRINIVASAN, Desikan
发明人： MUKHOPADHYAY, Suvhasis , BHATTACHARYA, Santanu , KUMAR, Vikas , SINGH, Kumar, Shakti , DUTTA, Arunava , SRINIVASAN, Desikan
IPC分类号： H04J3/16
CPC分类号： H04J3/047 , H04J3/1617 , H04J2203/0025 , H04Q2213/13003 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13178 , H04Q2213/13214 , H04Q2213/1332 , H04Q2213/13322
摘要： A multipacket interface is easily adaptable to any of several link layer interfaces via a simple adaptation layer which can be provided on an ASIC or FPGA. The interface according to the invention includes (in both transmit and receive directions) a multi-bit data signal, a multi-bit channel identifier, a packet abort/error signal, a start-of-frame signal, an end-of-frame signal, a data valid signal, and an interface clock, In the transmit direction, the interface also includes a data request signal and a multi-bit PDU length indicator signal. In the receive direction the interface also includes a server signal failure signal.
摘要翻译：多层接口可以通过可在ASIC或FPGA上提供的简单适配层轻松适应几个链路层接口中的任何一个。根据本发明的接口包括（在发送和接收方向上）多位数据信号，多位信道标识符，分组中止/错误信号，帧起始信号，帧结束信号，数据有效信号和接口时钟。在发送方向上，接口还包括数据请求信号和多位PDU长度指示符信号。在接收方向，接口还包括服务器信号故障信号。

64. 发明申请

WO2004073027A3 MICROPROCESSOR BASED SELF-DIAGNOSTIC PORT 审中-公开
公开(公告)号：WO2004073027A3
公开(公告)日：2004-08-26
申请号：PCT/US2004/003222
申请日：2004-02-05
申请人： TRANSWITCH CORPORATION
发明人： ABUHAMEDEH, Zahi, Said , PEARS, Philip, J.
IPC分类号： G01R31/28
摘要： An integrated circuit chip (10) is provided with a JTAG TAP (14), an on-chip JTAG master (16) coupled to the JTAG TAP and a microprocessor interface (20) coupled to the JTAG master. This arrangement permits testing the integrated circuit chip without removing it from a circuit board or taking the circuit board out of service. It allows testing without regard to other chips on the same board. Preferably, the chip also has a conventional JTAG interface which is switchably uncouplable from the JTAG TAP. Figure 1.

65. 发明申请

WO2004062201A1 METHOD AND APPARATUS FOR THE HARDWARE IMPLEMENTATION OF VIRTUAL CONCATENATION AND LINK CAPACITY ADJUSTMENT OVER SONET/SDH FRAMES 审中-公开
标题翻译：硬件实现硬件实现的方法和装置和SONET / SDH框架的链路容量调整
公开(公告)号：WO2004062201A1
公开(公告)日：2004-07-22
申请号：PCT/US2003/039892
申请日：2003-12-16
申请人： TRANSWITCH CORPORATION
发明人： CHONAN, Harpreet, S. , ROUAUD, Christophe
IPC分类号： H04L12/28
CPC分类号： H04J3/04 , H04J3/1617 , H04J2203/0069 , H04J2203/0094 , Y10S370/907
摘要： Methods and apparatus for the hardware implementation of virtual concatenation and link capacity adjustment over SONET/SDH frames include providing a state machine on chip with a SONET/SDH mapper and providing means whereby a plurality of members of a VCG can share the same state machine. The apparatus of the invention preferably includes a time wheel for granting access to the single state machine and memory for storing state information for each of the VCG members. According to the presently preferred embodiment, the invention is implemented on chip with an OC-3 Ethernet mapper. Up to eighty-four VCG members share the same state machine and memory is provided on the chip for maintaining the state information for eighty-four VCG members. Fifteen bits are used to store the state information for each VCG member in low order and seventeen bits are used to store the state information for each VCG member in high order.
摘要翻译：用于通过SONET / SDH帧进行虚级联和链路容量调整的硬件实现的方法和装置包括：使用SONET / SDH映射器提供芯片上的状态机，并提供由VCG的多个成员共享相同状态机的装置。本发明的装置优选地包括用于准许访问单个状态机的时间轮和用于存储每个VCG成员的状态信息的存储器。根据当前优选的实施例，本发明使用OC-3以太网映射器在芯片上实现。多达八十四个VCG成员共享相同的状态机，芯片上提供了内存，用于维护八十四个VCG成员的状态信息。十五位用于以低位存储每个VCG成员的状态信息，十七位用于以高阶存储每个VCG成员的状态信息。

66. 发明申请

WO2003040935A1 MULTIPORT NON-BLOCKING HIGH CAPACITY ATM AND PACKET SWITCH 审中-公开
标题翻译：多重非阻塞高容量ATM和分组交换机
公开(公告)号：WO2003040935A1
公开(公告)日：2003-05-15
申请号：PCT/US2002/032230
申请日：2002-10-09
申请人： TRANSWITCH CORPORATION
发明人： LIU, Zheng , AN, Jiu , XIAN, Terry , NOVICK, Ronald, P.
IPC分类号： G06F13/28
CPC分类号： G01N33/586
摘要： A multiport non-blocking high capacity ATM and packet switch (10) is a single chip switching solution for ATM and packet systems. It is capable of 8 x 8 switching of 800 Mbits/s per port (18) in both directions. The ports (18) support UTOPIA Level 2 interfaces. The switch (10) is non-blocking and lostless, incorporating a backpressure mechanism (40, 42, 46 and 48) for eliminating congestion toward any one port (18). The switch (10) supports prioritized and variable size cell and packet switching.
摘要翻译：多端口非阻塞高容量ATM和分组交换机10是用于ATM和分组系统的单芯片交换解决方案。它能够在两个方向上进行8×8切换，每个端口为800Mbits / s。端口18支持UTOPIA 2级接口。开关10是非阻塞的和无损的，包括用于消除任何一个端口18的拥塞的背压机构40,42,46和48.交换机10支持优先级和可变尺寸的小区和分组交换。

67. 发明申请

WO2002098087A1 METHOD AND APPARATUS FOR DESYNCHRONIZING A DS-3 SIGNAL AND/OR AN E3 SIGNAL FROM THE DATA PORTION OF AN STS/STM PAYLOAD 审中-公开
标题翻译：用于从STS / STM PAYLOAD的数据部分中分离DS-3信号和/或E3信号的方法和装置
公开(公告)号：WO2002098087A1
公开(公告)日：2002-12-05
申请号：PCT/US2002/014155
申请日：2002-05-06
申请人： TRANSWITCH CORPORATION
发明人： UPP, Daniel, C.
IPC分类号： H04L25/00
CPC分类号： H04J3/076 , H03L7/06
摘要： The desynchronizer (10) of the present invention includes two FIFOs. The first FIFO has two address counters (read and write), an intermediate count register (26), circuitry (for calculating the difference between the write and the intermediate counts and the intermediate and read counts, a logic block for performing pointer leak and other arithmetic functions and digitally controlled oscillator. The second FIFO has read and write counters, a phase-frequency detector (54), and an internal VCO (58) controlled by length measurements of the second FIFO. The desynchronizer (10) receives data bits, pointer movement indications, and stuff indications from a DS-3/E3 demapper and, using the first FIFO, the address counters, etc., removes the low frequency components, including SONET/SDH systemic gapping in order to provide the second FIFO with a DS-3/E3 signal having a high frequency phase modulation. The second FIFO removes the remaining high frequency gapping jitter.
摘要翻译：本发明的去同步器（10）包括两个FIFO。第一个FIFO有两个地址计数器（读和写），中间计数寄存器（26），用于计算写入和中间计数之间的差异以及中间和读取计数，用于执行指针泄漏的逻辑块等的电路算术功能和数字控制振荡器，第二FIFO具有读写计数器，相位检测器（54）和由第二FIFO的长度测量值控制的内部VCO（58），去同步器（10）接收数据位，指针移动指示和来自DS-3 / E3解映射器的填充指示，并且使用第一FIFO，地址计数器等，去除低频分量，包括SONET / SDH系统间隙，以便向第二FIFO提供一个具有高频相位调制的DS-3 / E3信号，第二个FIFO消除了剩余的高频间隙抖动。

68. 发明申请

WO2002079988A1 METHODS AND APPARATUS FOR BURST TOLERAN EXCESSIVE BIT ERROR RATE ALARM DETECTION AND CLEARING 审中-公开
标题翻译：用于BURST TOLERAN过度位错误率报警检测和清除的方法和装置
公开(公告)号：WO2002079988A1
公开(公告)日：2002-10-10
申请号：PCT/US2002/007974
申请日：2002-03-04
申请人： TRANSWITCH CORPORATION
发明人： SOLTYSIAK, Edward , SINGH, Kumar, Shakti , GOYAL, Pawan
IPC分类号： G06F11/00
CPC分类号： H04J3/14 , H04J2203/006 , H04L1/20 , Y10S370/907
摘要： The excessive bit error rate detection algorithm (Fig. 3) operates in tow modes (116): BURST mode (10 & 14) and non-BURST mode (10 & 12). In non-BURST mode (10 & 12), an alarm state (12) is entered if an error count (EC) exceeds (> =) a threshold (THDV) within a set number of frames and exits the alarm state (12) when the error count (EC) stays below a threshold (THDV) for a set number of frames. In the BURST mode (10 & 14), the alarm state (12) is not entered unless the error count (EC) exceeds the threshold (THDV) two consecutive times and does not exit the alarm state (12) unless the error (EC) remains below a threshold (THDV)for two consecutive frame counts.
摘要翻译：过多的误码率检测算法（图3）以拖曳模式（116）操作：BURST模式（10＆14）和非BURST模式（10＆12）。在非BURST模式（10和12）中，如果错误计数（EC）超过设定帧数（> =）阈值（THDV）并退出报警状态（12），则输入报警状态（12）当针对设定数量的帧时，错误计数（EC）保持低于阈值（THDV）。在BURST模式（10和14）中，除非错误计数（EC）连续超过阈值（THDV），否则不会输入报警状态（12），并且不会退出报警状态（12），除非错误（EC ）对于两个连续的帧计数保持低于阈值（THDV）。

69. 发明申请

WO1997043867A1 METHOD AND APPARATUS FOR PROVIDING MULTIPLE MULTICAST COMMUNICATION SESSIONS IN AN ATM DESTINATION SWITCH 审中-公开
标题翻译：用于在ATM目的地交换机中提供多个多播通信会话的方法和装置
公开(公告)号：WO1997043867A1
公开(公告)日：1997-11-20
申请号：PCT/US1997009098
申请日：1997-05-16
申请人： TRANSWITCH CORPORATION
发明人： TRANSWITCH CORPORATION , LAU, Joseph, C. , ROY, Subhash, C.
IPC分类号： H04Q11/00
CPC分类号： H04L49/3009 , H04L49/201 , H04L49/203 , H04L49/30 , H04L49/3081
摘要： An ATM destination switch (130) comprising an ATM layer device which includes an ATM layer interface (135), a processor (136) with an associated translation RAM (162), and an ATM layer to physical layer interface. The processor decodes incoming ATM cell to obtain a VPI/VCI, and provides additional routing information to the cell for multicasting. The cell with the additional routing information is forwarded to the physical layer device which has a header processor (160), a multicast indicator storage table, in the form of a bit map for storing output line indications and ATM line output interfaces (170). The header processor (160) receives the cell with the additional routing information, reads the routing information, accesses the multicast indicator storage table based on the routing information to determine which output lines the cell is to be provided, and controls the copying of the cell for each output lines so that it may be received at multiple destinations. Thus, an incoming cell which is to be multicast to multiple users will be multicasted using the single VPI/VCI.
摘要翻译：包括ATM层设备的ATM目的地交换机（130），其包括ATM层接口（135），具有相关联的转换RAM（162）的处理器（136）以及ATM层到物理层接口。处理器解码传入的ATM信元以获得VPI / VCI，并向小区提供附加的路由信息以进行组播。具有附加路由信息的小区被转发到具有用于存储输出线路指示和ATM线路输出接口（170）的位图形式的头部处理器（160），组播指示符存储表的物理层设备。标题处理器（160）接收具有附加路由信息的小区，读取路由信息，基于路由信息访问多播指示符存储表，以确定要提供小区的哪些输出线，并控制小区的复制对于每个输出线，使得其可以在多个目的地被接收。因此，将使用单个VPI / VCI来组播要多播到多个用户的传入小区。

70. 发明申请

WO1997012323A1 APPARATUS AND METHOD EMPLOYING A WINDOW RESET FOR EXCESSIVE BIT ERROR RATE ALARM DETECTION AND CLEARING 审中-公开
标题翻译：装置和方法使用窗口复位用于过大的位错误率报警检测和清除
公开(公告)号：WO1997012323A1
公开(公告)日：1997-04-03
申请号：PCT/US1996015587
申请日：1996-09-27
申请人： TRANSWITCH CORPORATION
发明人： TRANSWITCH CORPORATION , LAU, Joseph, C.
IPC分类号： G06F11/00
CPC分类号： H04L1/24 , H04L43/0847 , H04L43/16
摘要： Methods and apparatus for generating and clearing an excessive bit error rate alarm are provided and utilize a window algorithm. Data blocks of telecommunications signal are monitored in an "idle state" (12). A counter counts the number of incoming blocks in a window such that the block having a code violation count (CV) meeting or exceeding a threshold (CVSET) (14). If the count meets or exceeds its own threshold (x) (26), an alarm state is entered and an alarm is set (30). Otherwise, the system returns to the "idle state" (27). In the alarm state, a clearing counter (CC) counts the number of incomming blocks in the window having a CV of CVCLRR or less (34). If the CC count meets a third threshold value (Y) (45), the alarm is cleared and the system returns to the idle state. Otherwise, the system reverts to the alarm state (47).
摘要翻译：提供了产生和清除过度误码率报警的方法和装置，并利用窗口算法。在“空闲状态”（12）中监视电信信号的数据块。计数器对窗口中的输入块的数目进行计数，使得具有符合或超过阈值（CVSET）的代码违规计数（CV）的块（14）。如果计数满足或超过自己的阈值（x）（26），则输入报警状态并设置报警（30）。否则，系统返回到“空闲状态”（27）。在报警状态下，清算计数器（CC）对具有CVCLRR或更低CV的窗口中的进位块数进行计数（34）。如果CC计数满足第三个阈值（Y）（45），则报警被清除，系统返回到空闲状态。否则，系统恢复到报警状态（47）。

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