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61. 发明授权

US5059920A CMOS amplifier with offset adaptation 失效
标题翻译：具有偏移适配的CMOS放大器
公开(公告)号：US5059920A
公开(公告)日：1991-10-22
申请号：US525764
申请日：1990-05-18
申请人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
发明人： Janeen D. W. Anderson , Carver A. Mead , Timothy P. Allen , Michael F. Wall
IPC分类号： G06N3/063 , H01L27/06 , H03F1/02 , H03F1/30 , H03F3/45
CPC分类号： H03F1/0261 , G06N3/063 , H01L27/0629 , H03F1/303 , H03F3/45479 , H03F3/45753 , H03F3/45977
摘要： Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.An analog MOS integrated circuit comprises an amplifier circuit having a gain much larger than 1. The inverting input into one stage of this amplifier circuit is a floating node forming the gate of at least one MOS transistor. A first capacitor couples an input of the circuit to this floating node. Electrical semiconductor structures are provided for both linearly adding and removing charge from the floating gate, thus allowing the offset voltage of the amplifier to be adapted.An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An electrical learning means allows the floating node to be charged or discharged to a voltage which effectively cancels the input offset voltage.
摘要翻译：通过施加第一和第二电气控制信号，电子可以以模拟方式放置在与至少一个MOS晶体管（通常是晶体管的栅极）相关联的浮动节点上并从其移除。第一电控信号控制电子从电子注入结构注入到浮动节点上，第二电控信号通过电子去除结构控制从浮动节点去除电子。模拟MOS集成电路包括具有大于1的增益的放大器电路。该放大器电路的一级的反相输入是形成至少一个MOS晶体管的栅极的浮动节点。第一个电容将电路的输入耦合到该浮动节点。提供电气半导体结构用于从浮动栅极线性地添加和去除电荷，从而允许放大器的偏移电压被适配。具有随机输入偏移电压的集成电路放大器是可适应的，使得可以抵消输入偏移电压。反相输入节点是浮动输入节点，并通过第一电容器耦合到输入信号源。第二电容器连接在放大器的输出端和浮动节点之间。电学习装置允许浮动节点被充电或放电到有效地抵消输入偏移电压的电压。

62. 发明授权

US4876534A Scanning method and apparatus for current signals having large dynamic range 失效
标题翻译：具有较大动态范围的电流信号的扫描方法和装置
公开(公告)号：US4876534A
公开(公告)日：1989-10-24
申请号：US152894
申请日：1988-02-05
申请人： Carver A. Mead , Timothy P. Allen
发明人： Carver A. Mead , Timothy P. Allen
IPC分类号： H04N5/335 , H04N5/374 , H04N5/378
CPC分类号： H04N5/335
摘要： There is disclosed herein apparatus and a method for scanning information off a processing plane where the information is contained in a current signal having a very small amplitude and which can change signs and vary in amplitude by as much as five orders of magnitude. The preferred embodiment of the apparatus uses a pair of CMOS pass transistors connected to the individual processing elements and the row select lines. The pass transistors, when turned on, couple the output current from the processor containing the desired information to a column line. The column line is connected to a current to voltage converter in the form of a differential input amplifier having a non linear feedback circuit comprised of two diode connected CMOS transistors operating in the subthreshold region. The non linear feedback circuit provides an exponential transfer function which compresses the dynamic range of the output current from the processor to a smaller and more useable output range for an output voltage. The negative feedback to the inverting input coupled to the column line stabilizes the voltage on the column line to virtual ground thereby eliminating the delay associated with driving the parasitic capacitance of the column line with the very small output current from the processor in an attempt to substantially change the voltage of the column line.
摘要翻译：这里公开了一种用于从处理平面扫描信息的信息的方法，其中信息被包含在具有非常小幅度的当前信号中，并且可以改变符号并且在幅度上变化多达五个数量级。该装置的优选实施例使用连接到各个处理元件和行选择线的一对CMOS传输晶体管。传输晶体管在导通时将来自包含所需信息的处理器的输出电流耦合到列线。列线连接到具有非线性反馈电路的差分输入放大器形式的电流到电压转换器，该非线性反馈电路由在亚阈值区域中工作的两个二极管连接的CMOS晶体管组成。非线性反馈电路提供指数传递函数，其将来自处理器的输出电流的动态范围压缩到输出电压的较小且更可用的输出范围。耦合到列线的反相输入的负反馈将列线上的电压稳定到虚拟接地，从而消除与来自处理器的非常小的输出电流驱动列线的寄生电容相关的延迟，以试图基本上改变列线的电压。

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