会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 65. 发明专利
    • DE602005009794D1
    • 2008-10-30
    • DE602005009794
    • 2005-01-21
    • ST MICROELECTRONICS NVST MICROELECTRONICS SA
    • ROUAULT LUCILLECHAILLOU SYLVAINBOUTROS JOSEPH
    • H04B1/69H04L25/49
    • Method of decoding an incident UWB signal including successive incident pulses respectively received during successive Pulse Repetition Periods, each incident pulse including one transmitted symbol among M possible symbols, said transmitted symbol being corrupted by Inter Symbol Interferences (ISI), said method comprising the steps of: determining a correlation matrix (“), whose terms respectively represent the correlation between all the M possible symbols transmitted in a current Pulse Repetition Period, and at least in the previous and in the next Pulse Repetition Periods; performing a correlation between an incident current pulse received during a current PRP and the M possible symbols transmitted in said current PRP and at least in the previous and in the next PRPs for obtaining a correlation vector (Y); preprocessing said correlation vector (Y) including reducing the effect of the ISI from said correlation vector (Y) by using said correlation matrix (“); decoding said preprocessed correlation vector (Y") for obtaining the bits of the transmitted symbol included in said incident received current pulse.
    • 66. 发明专利
    • DE602004014092D1
    • 2008-07-10
    • DE602004014092
    • 2004-01-19
    • ST MICROELECTRONICS NVST MICROELECTRONICS SRL
    • ZORY JULIENSPEZIALI FILIPPO
    • H03M13/29H03M13/27H04B7/216
    • A method and device for handling write access conflicts in interleaving, in particular for high-throughput turbo decoding for wireless communication systems; the device comprises N interleaving buffers (CLk) that are respectively connected to N producers (PRk), an LLR distributor means and N single port target memories (TMk). At any time step, each interleaving buffer receives m LLR inputs from the producers and has to write up to M of these into a register bank (RBk), which comprises W registers. M denotes the maximum number of concurrent write operations supported per time step and W denotes the maximum buffer size. M and W are design parameters and are chosen for the standard case and not for the worst case. m-M producers have to be stalled whenever m is larger than M and m producers have to be stalled whenever a buffer overflow occurs (more than W LLR values). Finally, at any time step one LLR value is fetched from the register bank and written to the SRAM interleaving memory.