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61. 发明申请

WO1997025687A1 DISPLAY DEVICE 审中-公开
标题翻译：显示设备
公开(公告)号：WO1997025687A1
公开(公告)日：1997-07-17
申请号：PCT/JP1996003841
申请日：1996-12-27
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , SUGITA, Kazunari
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： G06K17/00
CPC分类号： G07F7/1008 , G06K7/0013 , G06K7/006 , G06Q20/341 , G07F7/08 , G07F7/0833 , G07F7/0886
摘要： A portable and easy-to-use display device (1) comprises a card sensor (4c) for detecting the loading/removal of an IC card (7), and a control unit (5) which, when the IC card (7) that is loaded is detected by the card sensor (4c), reads the balance data and the transaction history data from the IC card (7) and alternatingly displays them on a display unit (2). Upon simply loading the IC card (7) into the display device (1), the card sensor (4c) detects the IC card (7) that is loaded, and the control unit (5) reads the balance data and the transaction history data from the IC card (7) and alternatingly displays them on the display unit (2).
摘要翻译：一种便携式和易于使用的显示装置（1）包括用于检测IC卡（7）的装载/取出的卡传感器（4c），以及控制单元（5），当IC卡（7）通过卡传感器（4c）检测加载的信息，从IC卡（7）读取余额数据和交易历史数据，并将其交替地显示在显示单元（2）上。在将IC卡（7）简单地装载到显示装置（1）中时，卡传感器（4c）检测装载的IC卡（7），并且控制单元（5）读取余额数据和交易历史数据从IC卡（7）开始，并将其显示在显示单元（2）上。

62. 发明申请

WO1997007537A1 METHOD OF PRODUCING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：生产半导体器件的方法
公开(公告)号：WO1997007537A1
公开(公告)日：1997-02-27
申请号：PCT/JP1996002335
申请日：1996-08-21
申请人： ASM JAPAN K.K. , OKI ELECTRIC INDUSTRY CO., LTD. , KOIZUMI, Satoshi , YOSHIMARU, Masaki , MORI, Yukihiro , FUKUDA, Hideaki
发明人： ASM JAPAN K.K. , OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H01L21/316
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02274 , H01L21/31625 , H01L21/31629
摘要： A method of obtaining a highly reliable semiconductor device by decreasing hygroscopic property of an insulating film of SiOF. In manufacturing a semiconductor device using a fluorine-containing silicon oxide film as an interlayer insultating film, fluorine-containing silicon oxide film is formed in an atmosphere containing an inert gas (14) in addition to source gases (11 to 13).
摘要翻译：通过降低SiOF绝缘膜的吸湿性而获得高度可靠的半导体器件的方法。在制造使用含氟氧化硅膜作为夹层绝缘膜的半导体器件中，除了源气体（11〜13）之外，在含有惰性气体（14）的气氛中也形成含氟氧化硅膜。

63. 发明申请

WO1996008070A1 BOOSTER 审中-公开
公开(公告)号：WO1996008070A1
公开(公告)日：1996-03-14
申请号：PCT/JP1995001770
申请日：1995-09-06
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , MATSUSHITA, Yuichi
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H02M03/07
CPC分类号： H02M3/073
摘要： A booster circuit which generates a boosted voltage, which is higher than the power supply voltage, from the power supply voltage. The circuit is provided with two capacitors which alternately perform charging and discharging in response to the voltage at the input terminal of the circuit. The first and second capacitors respectively boost the voltages at the boosting node and output terminal of the circuit. The circuit is also provided with a control circuit which applies to the first capacitor such a voltage that causes the first capacitor to discharge after the second capacitor is fully charged when the voltage at the input terminal changes to an "L" level from an "H" level, so as to prevent the power supply voltage Vcc from being applied to the boosting node through a transistor which conducts in response to the voltage at the output terminal when the voltage at the output terminal drops due to the charging of the second capacitor. When the first capacitor discharges, the voltage at the boosting node is raised and the power supply voltage Vcc is applied to the output terminal through a transistor which conducts in response to the voltage at the boosting node. Therefore, the voltage at the output terminal can be raised to the power supply voltage Vcc.
摘要翻译：升压电路，从电源电压产生高于电源电压的升压电压。该电路设有两个电容器，它们响应于电路的输入端的电压而交替执行充电和放电。第一和第二电容器分别升高电路的升压节点和输出端子处的电压。该电路还设置有一个控制电路，该控制电路施加到第一电容器上，使得当输入端子上的电压从“H”变为“L”电平时，使第一电容器在第二电容器充满电之后放电 “电平，以便防止电源电压Vcc通过晶体管施加到升压节点，该晶体管响应于输出端子处的电压而导通，当输出端子处的电压由于第二电容器的充电而下降时。当第一电容器放电时，升压节点处的电压升高，并且通过响应于升压节点处的电压导通的晶体管将电源电压Vcc施加到输出端子。因此，可以将输出端子处的电压升高到电源电压Vcc。

64. 发明申请

WO1995010849A1 PATTERN AND METHOD FOR EVALUATING FOCAL POINT 审中-公开
标题翻译：用于评估焦点的图案和方法
公开(公告)号：WO1995010849A1
公开(公告)日：1995-04-20
申请号：PCT/JP1994001705
申请日：1994-10-12
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , WATANABE, Akira
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H01L21/027
CPC分类号： G03F7/70558 , G03F1/44 , G03F7/70633 , G03F7/70641
摘要： The pattern of a reticle having a fine pattern which is finer than the resolution of a stepper or a fine line pattern whose lines are separated from each other by distances shorter than the resolution of the stepper is transferred to various areas of the surface of a wafer, and the size of the pattern is measured. Consequently the best focusing position (in-focus wafer position) can be easily determined.
摘要翻译：具有比步进器分辨率精细的精细图案的标线图案或细线图案的线条彼此分开距离比步进机分辨率短的距离转印到晶片表面的各个区域，并测量图案的尺寸。因此，可以容易地确定最佳聚焦位置（聚焦晶片位置）。

65. 发明申请

WO1995001008A1 BIT ERROR COUNTING METHOD AND COUNTER 审中-公开
标题翻译：位错误计数方法和计数器
公开(公告)号：WO1995001008A1
公开(公告)日：1995-01-05
申请号：PCT/JP1993000830
申请日：1993-06-21
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , ABE, Masami
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H03M13/12
CPC分类号： H04L1/208 , H03M13/3961 , H03M13/41 , H03M13/6502 , H04L1/20
摘要： When Viterbi decoding of input signal is executed, the errors in the decoded signal must be counted. By conventional methods in which decoded signal is recoded and compared with the inputted signal to count the errors, it is impossible to count exactly the errors if some errors are produced in re-recording the input signal which contains a great number of errors. In order to solve this problem, the pathmetric value calculated during the Viterbi decoding, and then, this value is output as the number of errors. Two decoding devices each of which reads the pathmetric value and outputs this value as the number of errors are provided for voice signals and FACCH signals, respectively. A signal is inputted into these two devices, and decoded. The numbers of errors obtained respectively from them are compared. Based upon the result of this comparison, it is determined whether the inputted signal is a voice signal or an FACCH signal.
摘要翻译：当执行输入信号的维特比解码时，必须对解码信号中的误差进行计数。通过将解码信号重新编码并与输入的信号进行比较以对误差进行计数的常规方法，如果在重新记录包含大量错误的输入信号中产生一些错误，则不可能精确地计数错误。为了解决这个问题，在维特比解码期间计算出的路径测量值，然后将该值作为错误的数量输出。分别为语音信号和FACCH信号分别提供读取路径测量值并输出该值作为错误数量的两个解码装置。信号被输入到这两个装置中并进行解码。比较分别获得的误差数。基于该比较的结果，确定输入的信号是语音信号还是FACCH信号。

66. 发明申请

WO1994024672A1 CIRCUIT FOR DECODING VARIABLE-LENGTH CODE, AND SYSTEM FOR DECODING VARIABLE-LENGTH CODE WHICH USES THE CIRCUIT 审中-公开
标题翻译：用于解码可变长度代码的电路和用于解码使用电路的可变长度代码的系统
公开(公告)号：WO1994024672A1
公开(公告)日：1994-10-27
申请号：PCT/JP1994000646
申请日：1994-04-19
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , KOMOTO, Eiji , NAKAMURA, Takao
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： G11C15/04
CPC分类号： H03M7/425 , G11C11/005 , G11C15/00 , G11C15/04
摘要： A circuit comprising a pair of a CAM cell (10) for storing variable-length codes and a RAM cell (20) for storing data used for mask processing. This circuit further has an NMOS (30) which is connected between the CAM cell (10) and a match line ML, and cuts off the CAM cell (10) from the match line ML by use of the output of the RAM cell (20). The CAM cell (10) checks a code applied from the outside with the code stored in it. If these codes are agreed with each other, the CAM cell (10) outputs an H level signal which represents the agreement to the match line ML. If disagreed, it outputs an L level signal which represents the disagreement to the match line ML. If the CAM cell does not engage in the checking operation, the corresponding RAM cell (20) outputs an L level signal to turn off the NMOS (30). When the NMOS is turned off, the output from the CAM cell (10) is not transmitted to the match line ML.
摘要翻译：一种电路，包括用于存储可变长度码的一对CAM单元（10）和用于存储用于掩模处理的数据的RAM单元（20）。该电路还具有NMOS（30），其连接在CAM单元（10）和匹配线ML之间，并且通过使用RAM单元（20）的输出从匹配线ML切断CAM单元（10））。 CAM单元（10）使用存储在其中的代码检查从外部应用的代码。如果这些代码彼此一致，则CAM单元（10）将表示协议的H电平信号输出到匹配线ML。如果不同意，则输出表示与匹配线ML不一致的L电平信号。如果CAM单元不参与检查操作，则相应的RAM单元（20）输出L电平信号以关闭NMOS（30）。当NMOS关断时，来自CAM单元（10）的输出不被发送到匹配线ML。

67. 发明申请

WO1994017618A1 INSTANTANEOUS PHASE SENSITIVE DETECTOR AND GENERATOR FOR CLOCK REPRODUCING SIGNAL INSTALLED IN DELAY DETECTOR 审中-公开
标题翻译：用于延迟检测器安装的时钟重现信号的瞬态相敏感探测器和发生器
公开(公告)号：WO1994017618A1
公开(公告)日：1994-08-04
申请号：PCT/JP1993001904
申请日：1993-12-27
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , NAKAMURA, Seizo , IGUCHI, Yuji , KODAMA, Akinobu
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H04L27/22
CPC分类号： H03D13/002 , H03D13/00 , H04L7/0331 , H04L7/04 , H04L7/046 , H04L25/061 , H04L27/22
摘要： An instantaneous phase detector (3A) comprises logic circuits (31, 32, and 36), running average filters (34 and 35), and pi /2 phase shifting circuit (33). The inputted signal is divided into two. The phase of one of the inputted signals is shifted from the other by pi /2. By use of the two signals, the phase is accurately measured. The generator for clock reproducing signals comprises a magnitude comparator, a level setter, a locus classifier, and a timing controller. By counting the timing of the inputted signals, a clock reproducing signal is generated.
摘要翻译：瞬时相位检测器（3A）包括逻辑电路（31,32和36），运行平均滤波器（34和35）和pi / 2移相电路（33）。输入信号分为两个。一个输入信号的相位由另一个π/ 2移位。通过使用两个信号，准确测量相位。用于时钟再现信号的发生器包括幅度比较器，电平设定器，轨迹分类器和定时控制器。通过计数输入信号的定时，产生时钟再生信号。

68. 发明申请

WO1994011943A1 POWER SUPPLY VOLTAGE BOOSTER 审中-公开
标题翻译：电源电压升压器
公开(公告)号：WO1994011943A1
公开(公告)日：1994-05-26
申请号：PCT/JP1993001683
申请日：1993-11-17
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , MATSUI, Katsuaki , MIYAMOTO, Sampei , KIKUCHI, Hidekazu
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H02M03/07
CPC分类号： H02M3/073
摘要： A booster comprises first to fourth boosting circuits which receive first to fourth signals and provide first to fourth boosted potentials to first to fourth nodes, respectively; a first precharge circuit which is controlled by the fourth boosted potential of the fourth node in order to precharge a first node; a second precharge circuit which is controlled by the second boosted potential of the second node and precharges the third node; and a first output circuit which outputs the boosted potential to the first node. Since there is no voltage drop in each of the boosted potentials of the second and fourth nodes, it is possible to create a high potential difference in the first and third precharge circuits, and to output a specific boosted potential without lowering the speed at which the first and third nodes are precharged.
摘要翻译：升压器包括分别接收第一至第四信号并且分别向第一至第四节点提供第一至第四升压电位的第一至第四升压电路; 第一预充电电路，由第四节点的第四升压电位控制，以便为第一节点预充电; 第二预充电电路，由第二节点的第二升压电位控制并预充电第三节点; 以及将升压电位输出到第一节点的第一输出电路。由于在第二和第四节点的每个升压电位中没有电压降，所以可以在第一和第三预充电电路中产生高电位差，并且在不降低特定升压电位的情况下输出特定的升压电位第一和第三节点被预充电。

69. 发明申请

WO1994010705A1 INPUT/OUTPUT PROTECTIVE CIRCUIT 审中-公开
标题翻译：输入/输出保护电路
公开(公告)号：WO1994010705A1
公开(公告)日：1994-05-11
申请号：PCT/JP1993001557
申请日：1993-10-28
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , KATAKURA, Yoshiaki , FUKUDA, Yasuhiro
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H01L29/784
CPC分类号： H01L27/0251
摘要： The cathode of an input protective diode (40) is connected directly to the drain (30D) of an input protective MOS transistor (30). The source (30S), the gate (30G), and the anode of the input protection diode (40) are grounded. Thus, overvoltage inputted from the external terminal is received by the cathode of the diode (40) and the drain (30D) before such a voltage is transferred to the internal circuit of a semiconductor device. Hence there is no increase in the junction capacitance of the input protective diode due to the pattern of the diode (40). The voltage value at which the input protective MOS transistor (30) conducts can be lowered because the input protective diode (40) breaks down by overvoltage before it reaches the internal circuit. As a result, it is possible to achieve reliable input protection at a high speed. Also, since the input terminal can be connected directly to the drain (30D) of the input protective MOS transistor (30), the input protective circuit shown is applicable to an output protection circuit and an output MOS transistor, thus making it possible to protect the internal output circuit reliably.
摘要翻译：输入保护二极管（40）的阴极直接连接到输入保护MOS晶体管（30）的漏极（30D）。源极（30S），栅极（30G）和输入保护二极管（40）的阳极接地。因此，在将这样的电压传送到半导体器件的内部电路之前，从外部端子输入的过电压被二极管（40）的阴极和漏极（30D）接收。因此，由于二极管（40）的图案，输入保护二极管的结电容没有增加。由于输入保护二极管（40）在到达内部电路之前由于过电压而损坏，所以输入保护MOS晶体管（30）导通的电压值可能降低。结果，可以高速地实现可靠的输入保护。此外，由于输入端子可以直接连接到输入保护MOS晶体管（30）的漏极（30D），因此所示的输入保护电路可应用于输出保护电路和输出MOS晶体管，从而可以保护内部输出电路可靠。

70. 发明申请

WO1994006178A1 ELECTRIC CONNECTOR 审中-公开
标题翻译：电连接器
公开(公告)号：WO1994006178A1
公开(公告)日：1994-03-17
申请号：PCT/JP1993001259
申请日：1993-09-07
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , NIIMURA, Yuuji
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： H01R23/00
CPC分类号： G06K7/0026 , G06K7/0021 , H01R12/83
摘要： An electric connector (100) for establishing electric contact with a card-like medium having an electric connection terminal comprises a case (101) including a flat surface (102b) having first and second sides and a slope surface (102a) having third and fourth sides opposing each other, the fourth side being connected to the first side of the flat surface (102b), this slope surface (102a) inclining from the fourth side towards the third side; support means (152) so disposed as to oppose the slope surface (102a), for supporting a contact (104) disposed on the side of the slope surface (102a); and fixing means (109, 110) for fixing the card-like medium inserted between the slope surface and the contact (104) under the state where the electric connection terminal and the contact (104) are in contact with each other.
摘要翻译：用于与具有电连接端子的卡状介质建立电接触的电连接器（100）包括：壳体（101），包括具有第一和第二侧面的平坦表面（102b）和具有第三和第四侧面的倾斜表面（102a）所述第四侧与所述平坦面（102b）的第一面连接，所述倾斜面（102a）从所述第四面朝向所述第三面倾斜; 支撑装置（152），其设置成与斜面（102a）相对，用于支撑设置在倾斜表面（102a）一侧的接触件（104）; 以及用于在电连接端子和触头（104）彼此接触的状态下固定插入在倾斜表面和触点（104）之间的卡状介质的固定装置（109,110）。

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