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61. 发明申请

US20090199167A1 Hardware Definition Method 有权
标题翻译：硬件定义方法
公开(公告)号：US20090199167A1
公开(公告)日：2009-08-06
申请号：US12087916
申请日：2007-01-17
申请人： Martin Vorbach , Frank May
发明人： Martin Vorbach , Frank May
IPC分类号： G06F9/45 , G06F17/50 , G06F15/78
CPC分类号： G06F17/5045 , G06F17/5054
摘要： The invention relates to a method for defining hardware, in which a library of parameterizable, executable elements is provided, parameters are selected, the elements comprising selected parameters are compiled, and the compilation is then simplified.
摘要翻译：本发明涉及一种用于定义硬件的方法，其中提供可参数化的可执行元素库，参数被选择，包括所选参数的元素被编译，然后简化编译。

62. 发明申请

US20090100286A1 METHODS AND DEVICES FOR TREATING AND PROCESSING DATA 有权
标题翻译：用于处理和处理数据的方法和设备
公开(公告)号：US20090100286A1
公开(公告)日：2009-04-16
申请号：US12257075
申请日：2008-10-23
申请人： MARTIN VORBACH , VOLKER BAUMGARTE
发明人： MARTIN VORBACH , VOLKER BAUMGARTE
IPC分类号： G06F1/10
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.
摘要翻译：一种数据处理单元，具有可操作在不同配置状态的时钟逻辑单元（PAE）字段和用于预选逻辑单元时钟的时钟预选装置。时钟预选装置被设计成使得根据状态，至少在第一小区（PAE）预先选择第一时钟，并且至少在附加小区上预先选择附加时钟。

63. 发明授权

US07444531B2 Methods and devices for treating and processing data 有权
标题翻译：处理和处理数据的方法和装置
公开(公告)号：US07444531B2
公开(公告)日：2008-10-28
申请号：US10469909
申请日：2002-03-05
申请人： Martin Vorbach , Volker Baumgarte
发明人： Martin Vorbach , Volker Baumgarte
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.
摘要翻译：一种数据处理单元，具有可操作在不同配置状态的时钟逻辑单元（PAE）字段和用于预选逻辑单元时钟的时钟预选装置。时钟预选装置被设计成使得根据状态，至少在第一小区（PAE）预先选择第一时钟，并且至少在附加小区上预先选择附加时钟。

64. 发明申请

US20080191737A1 Reconfigurable sequencer structure 有权
公开(公告)号：US20080191737A1
公开(公告)日：2008-08-14
申请号：US12082073
申请日：2008-04-07
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： H03K19/173
CPC分类号： G06F15/7867 , G06F9/30145 , G06F13/16 , G06F13/36 , G06F13/4068 , H03K19/173
摘要： A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.

65. 发明申请

US20070299993A1 Method and Device for Treating and Processing Data 审中-公开
标题翻译：处理和处理数据的方法和装置
公开(公告)号：US20070299993A1
公开(公告)日：2007-12-27
申请号：US10469910
申请日：2002-03-05
申请人： Martin Vorbach , Volker Baumgarte , Armin Nuckel , Frank May
发明人： Martin Vorbach , Volker Baumgarte , Armin Nuckel , Frank May
IPC分类号： G06F3/00
CPC分类号： G06F15/17
摘要： Procedures and methods for managing and transmitting data within multidimensional systems of transmitters and receivers are described. Splitting a data stream into a plurality of independent branches and subsequent merging of the individual branches to form a data stream is to be performable in a simple manner, the individual data streams being recombined in the correct sequence. This method is of importance in particular for executing reentrant code. The method is well suited, in particular, for configurable architectures; particular attention is paid to the efficient control of configuration and reconfiguration.
摘要翻译：描述了在发射机和接收机的多维系统内管理和传输数据的过程和方法。将数据流分解成多个独立分支并且随后各个分支的合并以形成数据流可以以简单的方式执行，单个数据流以正确的顺序重新组合。该方法对于执行可重入码尤其重要。该方法特别适用于可配置架构; 特别注意配置和重新配置的有效控制。

66. 发明授权

US07243175B2 I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures 有权
标题翻译：用于DFP的I / O和内存总线系统以及具有两维或多维可编程单元架构的单元
公开(公告)号：US07243175B2
公开(公告)日：2007-07-10
申请号：US10792168
申请日：2004-03-02
申请人： Martin Vorbach , Robert Münch
发明人： Martin Vorbach , Robert Münch
IPC分类号： G11C7/10 , G06F15/76 , G06F15/78 , G06F15/80 , G06F17/10
CPC分类号： H03K19/17736 , G06F15/7867 , G11C7/10 , H03K19/17744 , H03K19/17796
摘要： A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).
摘要翻译：提供通用总线系统，其组合多个内部线路并将它们作为捆绑器连接到终端。总线系统控制是预定义的，不需要程序员的任何影响。任何数量的存储器，外设或其他单元都可以连接到总线系统（用于级联）。

67. 发明授权

US07174443B1 Run-time reconfiguration method for programmable units 有权
标题翻译：可编程单元的运行时重新配置方法
公开(公告)号：US07174443B1
公开(公告)日：2007-02-06
申请号：US09494567
申请日：2000-01-31
申请人： Martin Vorbach , Robert Münch
发明人： Martin Vorbach , Robert Münch
IPC分类号： G06F15/16 , G06F15/80
CPC分类号： G06F15/7867 , G06F9/24
摘要： A method of run-time reconfiguration of a programmable unit is provided, the programmable unit including a plurality of reconfigurable function cells in a multidimensional arrangement. An event is detected. The source of the detected event is determined, and an address of an entry in a jump table is calculated as a function of the source of the event, the entry storing a memory address of a configuration for a reconfigurable function cell. The entry is retrieved and a state of a corresponding reconfigurable cell is determined. If the reconfigurable cell is in a reconfiguration state, the reconfigurable cell is reconfigured as a function of the configuration data. If the reconfigurable cell in not in reconfiguration state, the configuration data is stored in a FIFO.
摘要翻译：提供了一种可编程单元的运行时重新配置的方法，所述可编程单元包括多维配置中的多个可重新配置的功能单元。检测到事件。确定检测到的事件的源，并且根据事件的源来计算跳转表中的条目的地址，该条目存储用于可重构功能单元的配置的存储器地址。检索条目并确定对应的可重构单元的状态。如果可重构单元处于重新配置状态，则可重构单元被重新配置为配置数据的函数。如果可重构单元未处于重新配置状态，则将配置数据存储在FIFO中。

68. 发明授权

US06859869B1 Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US06859869B1
公开(公告)日：2005-02-22
申请号：US09290342
申请日：1999-04-12
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F13/00 , G06F15/00 , G06F17/00
CPC分类号： G06F15/7867 , G06F2213/0038
摘要： A data processing system, wherein a data flow processor (DFP) integrated circuit chip is provided which comprises a plurality of orthogonally arranged homogeneously structured cells, each cell having a plurality of logically same and structurally identically arranged modules. The cells are combined and facultatively grouped using lines and columns and connected to the input/output ports of the DFP. A compiler programs and configures the cells, each by itself and facultatively-grouped, such that random logic functions and/or linkages among the cells can be realized. The manipulation of the DFP configuration is performed during DFP operation such that modification of function parts (MACROs) of the DFP can take place without requiring other function parts to be deactivated or being impaired.
摘要翻译：一种数据处理系统，其中提供了数据流处理器（DFP）集成电路芯片，其包括多个正交排列的均匀构造的单元，每个单元具有多个在逻辑上相同和结构上相同排列的模块。这些单元格使用线和列进行组合和分类，并连接到DFP的输入/输出端口。编译器编程和配置单元，每个单元本身并且被分组，使得可以实现单元之间的随机逻辑功能和/或连接。在DFP操作期间执行DFP配置的操作，以便可以对DFP的功能部件（MACRO）进行修改，而不需要禁用或损坏其他功能部件。

69. 发明授权

US06728871B1 Runtime configurable arithmetic and logic cell 有权
标题翻译：运行时可配置的算术和逻辑单元
公开(公告)号：US06728871B1
公开(公告)日：2004-04-27
申请号：US09329132
申请日：1999-06-09
申请人： Martin Vorbach , Robert Münch
发明人： Martin Vorbach , Robert Münch
IPC分类号： G06F1516
CPC分类号： G06F1/12 , G06F1/3203 , G06F1/3237 , G06F7/57 , G06F9/3001 , G06F9/30101 , G06F9/30134 , G06F9/3885 , G06F9/3897 , G06F15/7867 , Y02D10/126 , Y02D10/128 , Y02D50/20
摘要： A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is very small, which has positive effects on the space required and the configuration speed. Broadcasting is supported through the internal bus systems in order to distribute large volumes of data rapidly and efficiently. The ALU is equipped with a power-saving mode to shut down power consumption completely. There is also a clock rate divider which makes it possible to operate the ALU at a slower clock rate. Special mechanisms are available for feedback on the internal states to the external controllers.
摘要翻译：可以在功能和互连中配置的级联算术和逻辑单元（ALU）。在执行算法期间不需要解码命令。 ALU可以在运行时重新配置，而不会对周围的ALU，处理单元或数据流产生任何影响。配置数据量非常小，对所需的空间和配置速度有正面的影响。通过内部总线系统支持广播，以便快速有效地分发大量数据。 ALU配备了省电模式，完全关闭功耗。还有一个时钟分频器，可以以较慢的时钟速率操作ALU。可以使用特殊机制对外部控制器的内部状态进行反馈。

70. 发明授权

US06513077B2 I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures 有权
公开(公告)号：US06513077B2
公开(公告)日：2003-01-28
申请号：US09915213
申请日：2001-07-25
申请人： Martin Vorbach , Robert Münch
发明人： Martin Vorbach , Robert Münch
IPC分类号： G06F1300
CPC分类号： H03K19/17736 , G06F15/7867 , G11C7/10 , H03K19/17744 , H03K19/17796
摘要： A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

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