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61. 发明授权

US5827776A Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines 失效
标题翻译：制造集成电路的方法，其使用蚀刻停止件来产生交错的互连线
公开(公告)号：US5827776A
公开(公告)日：1998-10-27
申请号：US959106
申请日：1997-10-23
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/768 , H01L21/76816 , H01L23/5226 , H01L2924/0002
摘要： A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.
摘要翻译：提供了多层互连结构。多层互连结构包括根据一个示例性实施例形成的至少三层互连（导体）。三个导体中的两个导体在单独的垂直和水平平面中彼此交错。第三导体有利地在两个第二导体的至少一部分之间隔开横向距离。第三导体也被放置在第二导体的下方或可能的第二导体的上方，以减小它们之间的电容耦合。通过交错第二和第三导体，可以以最小的传播延迟和交叉耦合实现高密度互连。

62. 发明授权

US5804497A Selectively doped channel region for increased I.sub.Dsat and method for making same 失效
标题翻译：选择性掺杂通道区域用于增加IDat及其制备方法
公开(公告)号：US5804497A
公开(公告)日：1998-09-08
申请号：US695101
申请日：1996-08-07
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Fred N. Hause
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Fred N. Hause
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L21/70
CPC分类号： H01L29/66537 , H01L21/823807 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A selectively doped MOS transistor channel includes a deep impurity distribution and shallow impurity distribution. The deep impurity distribution is formed within high energy implant with an impurity of conductivity type opposite to the conductivity type of the source/drain regions of the transistor. In the n-channel regions, the deep impurity distribution preferably includes boron ions. The deep impurity distribution acts as a channel stop such that adjacent source/drain regions of the like type transistors are not inadvertently coupled during circuit operation. The shallow impurity distribution acts as a threshold implant by precisely controlling the doping of the transistor channel in the vicinity of the silicon oxide interface. The peak concentration of the shallow impurity distribution is located at a depth below the silicon surface which is greater than a depth typically associated with a threshold adjust implant. Because the impurity concentration of the shallow impurity distribution drops off rapidly from the peak concentration value, the concentration at the upper surface of the silicon substrate is not significantly greater than the doping of the silicon substrate itself. The light doping in the channel region of the transistor results in a substantially reduced threshold voltage for the transistor. Preferably, the threshold voltage of both the n-channel and p-channel devices has an absolute value of approximately 250 Mv. The lower threshold voltage translates into a higher I.sub.Dsat when the transistor is operated under normal conditions (e.g., V.sub.Gs =3 volts, V.sub.Ds =3 volts, and V.sub.sb =0 volts.)
摘要翻译：选择掺杂的MOS晶体管沟道包括深杂质分布和浅杂质分布。深度杂质分布形成在高能量注入内，其杂质的导电类型与晶体管的源/漏区的导电类型相反。在n沟道区域中，深杂质分布优选包括硼离子。深杂质分布充当通道阻挡，使得类似晶体管的相邻源极/漏极区在电路操作期间不会无意中耦合。通过精确地控制在氧化硅界面附近的晶体管沟道的掺杂，浅杂质分布充当阈值注入。浅杂质分布的峰值浓度位于硅表面下方的深度，该深度大于通常与阈值调整植入物相关联的深度。由于浅杂质分布的杂质浓度从峰值浓度值迅速下降，所以硅衬底上表面的浓度不会明显大于硅衬底本身的掺杂。在晶体管的沟道区域中的轻掺杂导致晶体管的阈值电压显着降低。优选地，n沟道和p沟道器件的阈值电压具有约250Mv的绝对值。当晶体管在正常条件下操作时（例如，VGs = 3V，VDs = 3V，Vsb = 0V），较低的阈值电压转换为更高的IDat。

63. 发明授权

US5795809A Semiconductor wafer fabrication process including gettering utilizing a combined oxidation technique 失效
标题翻译：半导体晶片制造工艺包括使用组合氧化技术的吸气
公开(公告)号：US5795809A
公开(公告)日：1998-08-18
申请号：US450021
申请日：1995-05-25
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Said N. Ghneim
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Said N. Ghneim
IPC分类号： H01L21/32 , H01L21/76
CPC分类号： H01L21/32
摘要： An improved method of silicon wafer fabrication suitable for either CMOS and/or NMOS process flows. The present method utilizes few processing steps to reduce fabrication costs and enhance wafer throughput. The improved method combines sacrificial oxide growth and removal steps of CMOS and NMOS front end pre-oxide steps with existing pad oxide growth and removal steps, resulting in fewer required operations. The thermal cycles required to form gettering sites within Cz bulk silicon wafers are retained, thus allowing the number of required processing operations to be reduced without negatively impacting existing levels of expected production yields.
摘要翻译：一种适用于CMOS和/或NMOS工艺流程的改进的硅晶片制造方法。本方法利用很少的处理步骤来降低制造成本并提高晶片产量。改进的方法将CMOS和NMOS前端预氧化物步骤的牺牲氧化物生长和去除步骤与现有的衬垫氧化物生长和去除步骤相结合，导致较少的所需操作。保留在Cz体硅片中形成吸气位置所需的热循环，从而允许减少所需的加工操作的数量，而不会不利地影响预期生产产量的现有水平。

64. 发明授权

US5783481A Semiconductor interlevel dielectric having a polymide for producing air gaps 失效
标题翻译：具有用于产生气隙的聚酰亚胺的半导体层间电介质
公开(公告)号：US5783481A
公开(公告)日：1998-07-21
申请号：US659167
申请日：1996-06-05
申请人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
发明人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44 , H01L21/48
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L2924/0002
摘要： A dielectric material is provided having air gaps which form during dielectric deposition between horizontal or vertical spaced conductors. The dielectric is deposited upon a polyimide, wherein the polyimide is placed over and between an underlying level of conductors. As the overlying dielectric is deposited on the polyimide, the polyimide material outgasses to form air separation between the polyimide and dielectric. Air separation is particularly prevalent in regions between closely spaced conductors and in high elevational areas directly above each conductor. The dielectric deposition process preferably includes two deposition cycles. A first deposition temperature is used to force significant outgassing, and a second deposition cycle is needed to close any and all keyhole openings which might exist between closely spaced conductors. A combination of polyimide, air gaps (air-filled cavities) and deposited dielectric forms an inter-level dielectric structure having a low dielectric permittivity or dielectric constant in critical conductor spaces.
摘要翻译：提供介电材料，其具有在水平或垂直间隔的导体之间的介电沉积期间形成的气隙。电介质沉积在聚酰亚胺上，其中聚酰亚胺被放置在下面的导体层之上和之间。当覆盖的电介质沉积在聚酰亚胺上时，聚酰亚胺材料脱气形成聚酰亚胺和电介质之间的空气分离。空气分离在紧密间隔的导体之间的区域和每个导体正上方的高高度区域中是特别普遍的。介电沉积工艺优选包括两个沉积循环。使用第一沉积温度来强制显着的除气，并且需要第二沉积循环来封闭可能存在于紧密间隔的导体之间的任何和所有键孔。聚酰亚胺，气隙（充气腔）和沉积的电介质的组合形成在临界导体空间中具有低介电常数或介电常数的层间电介质结构。

65. 发明授权

US5445975A Semiconductor wafer with enhanced pre-process denudation and process-induced gettering 失效
标题翻译：半导体晶片具有增强的预处理剥蚀和工艺引起的吸气
公开(公告)号：US5445975A
公开(公告)日：1995-08-29
申请号：US206977
申请日：1994-03-07
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derick J. Wristers
IPC分类号： H01L21/322 , H01L21/324
CPC分类号： H01L21/3225 , Y10S148/06
摘要： A method is provided for pre-process denudation and process-induced gettering of a CZ silicon wafer having one or more monolithic devices embodied therein. Pre-process denudation is performed in a hydrogen ambient to out-diffuse oxygen as well as to maintain interstitial silicon flux away from the substrate surface. Process-induced gettering is performed at a low temperature to ensure stacking faults and surface irregularities do not arise from interstitial silicon bonding at the surface prior to gate oxidation. The third step of the denudation/gettering cycle involving precipitate growth is thereby delayed or forestalled until the field oxide is grown. Any changes or movement in oxygen and/or interstitial silicon within or near the substrate surface occurring after polysilicon deposition will have minimal effect upon the established gate oxide. Accordingly, gate oxide integrity (e.g., breakdown voltage and uniformity) are enhanced by the present process.
摘要翻译：提供了一种用于预处理剥蚀和具有其中实施的具有一个或多个单片器件的CZ硅晶片的工艺诱导吸除的方法。在氢环境中进行预处理剥蚀以使氧扩散以及保持间隙硅熔剂远离衬底表面。在低温下进行过程诱导的吸气以确保堆垛层错，并且在栅极氧化之前的表面处的间隙硅键不会产生表面不规则性。涉及沉淀生长的剥蚀/吸除循环的第三步骤因此被延迟或预防，直到场氧化物生长。在多晶硅沉积之后发生的衬底表面内或附近的氧和/或间隙硅中的任何变化或移动对所建立的栅极氧化物的影响最小。因此，通过本方法增强栅极氧化物完整性（例如，击穿电压和均匀性）。

66. 发明授权

US06451657B1 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant 失效
标题翻译：具有由横向扩散的氮植入物限定的超短沟道长度的晶体管
公开(公告)号：US06451657B1
公开(公告)日：2002-09-17
申请号：US09781044
申请日：2001-02-08
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28132 , Y10S257/90
摘要： A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region. Portions of the gate conductor layer not covered by the oxide mask are then removed, leaving the reduced-width nitrogen free region as a gate conductor having a width below the photolithography threshold.
摘要翻译：公开了一种用于制造具有小于使用普通光刻技术可分辨长度的沟道长度的晶体管的工艺。在轻掺杂的半导体衬底上形成栅氧化层。然后在栅极氧化物层上沉积栅极导体层。栅极导体层的上表面包括由间隔开的一对目标区域横向限定的未来导体区域，其中间隔开的一对目标区域之间的横向距离优选地以光刻阈值选择。将氮气注入到间隔开的一对目标区域中，以在栅极导体层内形成间隔开的一对含氮区域，从而在栅极导体层中限定无氮区域。热退火降低了无氮区域的宽度。然后在整个半导体拓扑上生长可变厚度的氧化物层，并进行各向异性蚀刻，以在较宽的无氮区域上形成氧化物掩模。然后去除不被氧化物掩模覆盖的栅极导体层的部分，留下宽度窄的无氮区域作为宽度低于光刻阈值的栅极导体。

67. 发明授权

US06326298B1 Substantially planar semiconductor topography using dielectrics and chemical mechanical polish 有权
标题翻译：使用电介质和化学机械抛光的基本平面的半导体形貌
公开(公告)号：US06326298B1
公开(公告)日：2001-12-04
申请号：US09513293
申请日：2000-02-25
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L214763
CPC分类号： H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
摘要翻译：一种用于形成具有全局平坦化的上表面的多层互连结构的方法。电介质沉积在半导体上以最小化形貌高度上的先前存在的差异并产生具有比下部区域更高的抛光速率的上表面形貌。随后的化学机械抛光产生基本平坦的表面。

68. 发明授权

US06258646B1 CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof 有权
标题翻译： CMOS集成电路和用于在注入PMOS晶体管区域之前注入NMOS晶体管区域以优化其热扩散率的方法
公开(公告)号：US06258646B1
公开(公告)日：2001-07-10
申请号：US09149631
申请日：1998-09-08
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L218238
CPC分类号： H01L27/092 , H01L21/823814 , Y10S257/90
摘要： A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.
摘要翻译：提出一种用于形成LDD结构的晶体管和晶体管制造方法，其中在形成p型掺杂剂之前形成与n沟道晶体管相关联的n型掺杂剂。 n型源极/漏极和LDD植入物通常需要比p型源极/漏极和LDD植入物更高的活化能（热退火）。首先在LDD工艺形成中执行具有最低扩散率并且需要最高温度退火的n型砷源/漏极注入。首先进行这样的高温退火可确保随后的更多移动式植入物的最小额外迁移。与更轻和较不密集的种植体物种相关的移植植入物在通道周边附近的LDD区域是普遍的。通过将后续退火步骤调整到低于源极/漏极退火步骤的温度，使得这些植入物进入通道的可能性降低。

69. 发明授权

US06200865B1 Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate 有权
标题翻译：使用牺牲介电结构形成具有自对准阈值的半导体器件调整并覆盖低电阻栅极
公开(公告)号：US06200865B1
公开(公告)日：2001-03-13
申请号：US09205443
申请日：1998-12-04
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21336
CPC分类号： H01L29/66537 , H01L21/28273 , H01L29/42324 , H01L29/66545 , H01L29/6659 , H01L29/66825
摘要： A semiconductor device is provided and formed using self-aligned low-resistance gates within a metal-oxide semiconductor (MOS) process. A sacrificial dielectric gate structure is formed on a semiconductor substrate instead of a conventional gate dielectric/gate conductor stack. After forming junction regions within a semiconductor substrate, the gate structure is removed to form a trench within a dielectric formed above the substrate. A low-resistance gate material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The gate material can take various forms, including a single layer or multiple metal and/or dielectric layers interposed throughout the as-filled trench. The gate formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.
摘要翻译：在金属氧化物半导体（MOS）工艺中，使用自对准的低电阻栅极提供并形成半导体器件。在半导体衬底上形成牺牲电介质栅极结构，而不是传统的栅极介质/栅极导体堆叠。在半导体衬底中形成结区之后，去除栅极结构，以在衬底之上形成的电介质内形成沟槽。然后可以在沟槽内，即在去除栅极导体的区域中布置低电阻栅极材料。栅极材料可以采取各种形式，包括插入整个填充沟槽中的单层或多个金属和/或介电层。栅极形成发生在高温循环之后，通常与激活以前注入的结或生长的栅极电介质相关联。因此，可以使用诸如铜或铜合金的低温金属。

70. 发明授权

US06188114B1 Method of forming an insulated-gate field-effect transistor with metal spacers 有权
标题翻译：用金属间隔物形成绝缘栅场效应晶体管的方法
公开(公告)号：US06188114B1
公开(公告)日：2001-02-13
申请号：US09204016
申请日：1998-12-01
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L31119
CPC分类号： H01L29/41783 , H01L29/41775 , H01L29/66575 , H01L29/6659
摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.
摘要翻译：公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。金属间隔物还可以提供低电阻漏极和源极触点。

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