专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明专利

AU2271097A High-power ampliflier using parallel transistors 未知
公开(公告)号：AU2271097A
公开(公告)日：1997-09-02
申请号：AU2271097
申请日：1997-02-13
申请人： GLENAYRE ELECTRONICS INC
发明人： WALKER MARK A
IPC分类号： H03F3/193 , H03F3/21 , H03F3/68 , H03F3/191
摘要： An input radio frequency signal to be amplified is fed to the gate terminals of parallel field effect power transistors through impedance matching networks that comprise parallel resistor-capacitor combinations. The capacitor is selected so that it is self-resonant at the frequency of operation, thereby preventing attenuation of the input signal at that frequency. A shunt resistor is coupled between the gates of the parallel transistors to eliminate odd mode oscillations.

62. 发明专利

IN179076B Paging system 未知
公开(公告)号：IN179076B
公开(公告)日：1997-08-23
申请号：IN517CA1993
申请日：1993-09-06
申请人： GLENAYRE ELECTRONICS INC
发明人： FAWCETT GLENN STUART , GLESSNER DAVID WAYNE , WITSAMAN MARK LEONARD
IPC分类号： G04G7/02

63. 发明专利

AU7483196A Paging system using compact hierarchical addressing 未知
公开(公告)号：AU7483196A
公开(公告)日：1997-06-05
申请号：AU7483196
申请日：1996-11-01
申请人： GLENAYRE ELECTRONICS INC
发明人： FAWCETT GLENN S
IPC分类号： H04W88/18 , H04Q7/14
摘要： An hierarchical addressing mechanism for use in a paging system is disclosed. The paging system assigns a compressed organization identifier to each of the organization identifiers for the organizations that are sharing the resources of the paging system. Each of the pagers within the paging system are provided with an associative table that associates the compressed organization identifiers with organization identifiers. In operation, the paging system forms a page by appending an address word to a message. The address word includes the compressed organization identifier determined from the associative table and the pager identifier for the called pager. In this manner, a more efficient method of addressing pagers is disclosed.

64. 发明专利

FI965244A 未知
公开(公告)号：FI965244A
公开(公告)日：1997-02-26
申请号：FI965244
申请日：1996-12-30
申请人： GLENAYRE ELECTRONICS INC
发明人： MARCHETTO ROBERT F , STEWART TODD A , HO PAUL KAR-MING
IPC分类号： H04B7/005 , H04B
摘要： A method and apparatus for compensating fading and interference in a radio signal. A plurality of pilot symbols are appended to a plurality of data symbols to form successive frames that are modulated at a transmitter. The transmitted modulated signal is subject to loss of data due to simple fading and multi-path and simulcast interference. The received signals are demodulated by a receiver and processed to provide a data signal comprising the data symbols and a pilot signal comprising the pilot symbols. The data signal is delayed for sufficient time to enable channel impulse response estimates to be made of successive blocks of pilot symbols, preferably using pilot symbol blocks that both precede and follow the data symbols in the frame being processed. The channel impulse response estimates for blocks of pilot symbols are buffered and used by an interpolator to determine an interpolated channel impulse response estimate for each data symbol as a function of both the pilot symbols and of predefined channel characteristics. The interpolated channel impulse response estimates are applied to successive data symbols in the delayed data signal, enabling the data to be decoded, compensating for fading and interference. Interpolation using predefined channel characteristics based on worst case conditions substantially improves the bit error rate (BER) for the data recovered, compared to the prior art.

65. 发明专利

AU3594995A High power radio frequency divider/combiner 未知
公开(公告)号：AU3594995A
公开(公告)日：1996-04-09
申请号：AU3594995
申请日：1995-09-20
申请人： GLENAYRE ELECTRONICS INC
发明人： FREDERICK THOMAS L , JONES DAVID E
IPC分类号： H01P5/16 , H05K1/02 , H05K1/18 , H01P5/12
摘要： An N-way power divider/combiner having isolated outputs using printed circuit board geometry that forms a ring of power resistors and output tramsmission lines spiraling around the ring to reduce the size of the circuit is disclosed. Both sides of the printed circuit board are used to achieve further size advantages. The invention thus provides a high-power radio frequency divider/combiner circuit that is much smaller than previous circuits that are able to handle equivalent power levels.

66. 发明专利

AU7253694A Compensation for multi-path interference using pilot symbols 未知
公开(公告)号：AU7253694A
公开(公告)日：1996-01-25
申请号：AU7253694
申请日：1994-06-30
申请人： GLENAYRE ELECTRONICS INC
发明人： MARCHETTO ROBERT F , STEWART TODD A , HO PAUL KAR-MING
IPC分类号： H04B7/005 , H03D1/00 , H04L27/06 , H04B1/10 , G06F11/10 , H03M13/12
摘要： A method and apparatus for compensating fading and interference in a radio signal. A plurality of pilot symbols are appended to a plurality of data symbols to form successive frames that are modulated at a transmitter. The transmitted modulated signal is subject to loss of data due to simple fading and multi-path and simulcast interference. The received signals are demodulated by a receiver and processed to provide a data signal comprising the data symbols and a pilot signal comprising the pilot symbols. The data signal is delayed for sufficient time to enable channel impulse response estimates to be made of successive blocks of pilot symbols, preferably using pilot symbol blocks that both precede and follow the data symbols in the frame being processed. The channel impulse response estimates for blocks of pilot symbols are buffered and used by an interpolator to determine an interpolated channel impulse response estimate for each data symbol as a function of both the pilot symbols and of predefined channel characteristics. The interpolated channel impulse response estimates are applied to successive data symbols in the delayed data signal, enabling the data to be decoded, compensating for fading and interference. Interpolation using predefined channel characteristics based on worst case conditions substantially improves the bit error rate (BER) for the data recovered, compared to the prior art.

67. 发明专利

FI943415A0 未知
公开(公告)号：FI943415A0
公开(公告)日：1994-07-19
申请号：FI943415
申请日：1994-07-19
申请人： GLENAYRE ELECTRONICS INC
发明人： MARCHETTO ROBERT FRANK , STEWART TODD ALAN
IPC分类号： H04H20/67 , H04L25/38 , H04L27/12 , H04L27/152 , H04L , H04Q
摘要： A modem for use in a simulcast paging system includes a modulator (26) and a demodulator (30), both of which produce very low jitter, enabling the modem to be used at data rates well in excess of 1,200 baud. Both the modulator and the demodulator are implemented in software using a digital signal processor (DSP) (66). The modulator initially samples a non-return-to-zero (NRZ) input at a sample rate of 19.2 KHz, interpolates transitions between logic levels, and produces a frequency shift keyed (FSK) modulated signal at a center frequency different than that used for transmitting the modulated signal. Using an interpolation timer that responds to changes in logic level on the input, the modulator changes the frequency of the FSK modulated signal at the appropriate time with much greater accuracy than would be possible without interpolation. The FSK modulated signal is filtered to substantially attenuate frequencies outside a 3 KHz bandwidth, producing a filtered signal. By frequency shifting the filtered signal (either up or down) to a center frequency of approximately 1,700 Hz, interference between positive and negative frequencies is substantially eliminated. A digital-to-analog converter (DAC) (74) produces an analog FSK modulated signal. At a receiving modem (29), the demodulator digitizes the FSK modulated signal at a 19.2 KHz sample rate and shifts the digitized modulated signal to a center frequency of 0 Hz, producing a complex baseband comprising in-phase (real) and quadrature (imaginary) components. The DSP determines the instantaneous phase of the complex baseband signal, and from the time derivative of the instantaneous phase, determines its frequency. The instantaneous frequency is interpolated at eight times the major sample rate, producing an interpolated frequency signal so that changes in the sign of the interpolated frequency can be used to determine the logic level and zero crossing of the demodulated signal with greater resolution, substantially reducing jitter. Correlation of the demodulated signal at the data rate further reduces jitter.

68. 发明专利

FI943415A 未知
公开(公告)号：FI943415A
公开(公告)日：1994-07-19
申请号：FI943415
申请日：1994-07-19
申请人： GLENAYRE ELECTRONICS INC
发明人： MARCHETTO ROBERT FRANK , STEWART TODD ALAN
IPC分类号： H04H20/67 , H04L25/38 , H04L27/12 , H04L27/152 , H04L , H04Q
摘要： A modem for use in a simulcast paging system includes a modulator (26) and a demodulator (30), both of which produce very low jitter, enabling the modem to be used at data rates well in excess of 1,200 baud. Both the modulator and the demodulator are implemented in software using a digital signal processor (DSP) (66). The modulator initially samples a non-return-to-zero (NRZ) input at a sample rate of 19.2 KHz, interpolates transitions between logic levels, and produces a frequency shift keyed (FSK) modulated signal at a center frequency different than that used for transmitting the modulated signal. Using an interpolation timer that responds to changes in logic level on the input, the modulator changes the frequency of the FSK modulated signal at the appropriate time with much greater accuracy than would be possible without interpolation. The FSK modulated signal is filtered to substantially attenuate frequencies outside a 3 KHz bandwidth, producing a filtered signal. By frequency shifting the filtered signal (either up or down) to a center frequency of approximately 1,700 Hz, interference between positive and negative frequencies is substantially eliminated. A digital-to-analog converter (DAC) (74) produces an analog FSK modulated signal. At a receiving modem (29), the demodulator digitizes the FSK modulated signal at a 19.2 KHz sample rate and shifts the digitized modulated signal to a center frequency of 0 Hz, producing a complex baseband comprising in-phase (real) and quadrature (imaginary) components. The DSP determines the instantaneous phase of the complex baseband signal, and from the time derivative of the instantaneous phase, determines its frequency. The instantaneous frequency is interpolated at eight times the major sample rate, producing an interpolated frequency signal so that changes in the sign of the interpolated frequency can be used to determine the logic level and zero crossing of the demodulated signal with greater resolution, substantially reducing jitter. Correlation of the demodulated signal at the data rate further reduces jitter.

69. 发明专利

AU5012293A Digital simulcast transmission system 未知
公开(公告)号：AU5012293A
公开(公告)日：1994-03-15
申请号：AU5012293
申请日：1993-08-13
申请人： GLENAYRE ELECTRONICS INC
发明人： WITSAMAN MARK L , BENZ ROGER EUGENE , GLESSNER DAVID W , CROWLEY-DIERKS JOEL R , FAWCETT GLENN S
IPC分类号： H04H20/67 , H04W84/02 , H04M11/00
摘要： A simulcast system for broadcasting the same signal for a number of spaced-apart broadcast sites is disclosed. The system (20) of this invention includes a hub (28) adapted to receive the signal to be simulcast and a number of stations (30) that actually broadcast the signal. The hub places the digital signal packets referred to as PDBs (36). As pan of the signal packetization process, the hub evaluates the rate at which the signals should be broadcast and assigns a start time at which the signals should be broadcast; this information is attached to the PDBs. After a PDB is created it is forwarded to the stations over a link channel. Each station includes a station controller (32) and a station transmitter (34). The station controller, upon receiving a PDB, forwards the signal therein to the transmitter at the start time indicated and at the appropriate broadcast rate. All of the stations transmitting the signals contained within a single PDB do so based on the start time and broadcast rate information contained in that PDB. Consequently, each station broadcasts the same signals at the same time and at the same rate so as to ensure their simultaneous transmission.

70. 发明专利

FI931421A 未知
公开(公告)号：FI931421A
公开(公告)日：1993-10-01
申请号：FI931421
申请日：1993-03-30
申请人： GLENAYRE ELECTRONICS INC
发明人： WITSAMAN MARK L , GLESSNER DAVID W , BENZ ROGER E , CROWLEY-DIERKS JOEL R
IPC分类号： G04G7/02
摘要： A clock synchronization system for synchronizing the performance of a number of clocks (46) so that they run parallel with a reference clock is disclosed. Each clock of this synchronization system includes a counter (52) that indicates the current time and that is sequentially incremented by a counter advance signal applied thereto. A time counter controller (54) both initializes the counter and generates the clocking signal that controls the advancement of the counter. The time counter controller further monitors the time indicated by the counter and compares it to a reference-time signal received from a reference clock. Based on the comparison, the time counter controller selectively reinitializes the counter and adjusts the rate at which the clocking signal is applied to the counter so as to ensure that the counter advances at a rate equal to the rate at which the reference clock advances. In some versions of the invention, the comparison of the reference-time signal to the actual clock counter time is made at a maintenance operation point (58) remote from the clock. In these versions of the invention, the maintenance operation point reports the difference in the two times back to the time counter controller, which, in turn, makes the appropriate adjustments to the counter and to the clocking signal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式