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61. 发明专利

DE10242886B4 未知
公开(公告)号：DE10242886B4
公开(公告)日：2006-09-28
申请号：DE10242886
申请日：2002-09-16
申请人： ELPIDA MEMORY INC
发明人： TAKAI YASUHIRO
IPC分类号： G11C11/407 , H04L7/033 , G06F1/10 , G06F1/12 , G11C8/00 , G11C11/4076 , H03K5/13 , H03K5/131 , H03K5/15 , H03L7/081 , H03L7/089
摘要： Disclosed is an interpolating circuit for producing an output signal having a delay time corresponding to a value obtained by performing interior division of a phase difference between entered first and second signals by a preset interior division ratio. The interpolating circuit includes a waveform synthesis unit and a bias control unit. The waveform synthesis unit includes an OR gate, which receives the first and second signals, for outputting the logic OR between these two signals; a first switch element inserted between a node, which is connected to an output terminal, and a first power supply and turned on and off by the output signal of the OR gate; a series circuit comprising a first constant-current source and a second switch element turned on and off by the first signal; and a series circuit comprising a second constant-current source and a third switch element turned on and off by the second signal; the series circuits being connected in parallel between the output node and a second power supply. On the basis of control signals that decide the interior division ratio, the bias control unit performs control in such a manner that current-path switches are turned on and off so that first and second current values, which are the totals of current values, will flow into the first and second constant-current sources, respectively.

62. 发明专利

DE102006000618A1 未知
公开(公告)号：DE102006000618A1
公开(公告)日：2006-08-17
申请号：DE102006000618
申请日：2006-01-02
申请人： ELPIDA MEMORY INC
发明人： FUJI YUKIO
IPC分类号： G11C13/02
摘要： Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.

63. 发明专利

DE102004003618A8 未知
公开(公告)号：DE102004003618A8
公开(公告)日：2006-08-10
申请号：DE102004003618
申请日：2004-01-16
申请人： ELPIDA MEMORY INC , HITACHI ULSI SYSTEMS CO , HITACHI LTD
发明人： KITAMURA EIJI , YAMADA SATORU , KATO YOSHIKI , SAINO KANTA , SAITO MASAYOSHI , IIJIMA SHINPEI , OYU KIYONORI
IPC分类号： H01L21/336 , H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
摘要： Production of a semiconductor device comprises successively forming a gate insulating film, a polysilicon layer, a barrier film and a metal film on a semiconductor substrate, etching the metal film, the barrier film and polysilicon layer to form a gate electrode, nitriding the gate electrode at 700-950 [deg] C in an ammonia atmosphere, and selectively oxidizing to oxidize the polysilicon layer and silicon in the substrate without oxidizing the metal film. An independent claim is also included for a semiconductor device produced as described.

64. 发明专利

DE69832015D1 未知
公开(公告)号：DE69832015D1
公开(公告)日：2005-12-01
申请号：DE69832015
申请日：1998-07-31
申请人： ELPIDA MEMORY INC
发明人： TAMAKI SATOSHI
IPC分类号： G01R31/3185 , G01R31/28 , G06F11/22 , G11C29/02 , G11C29/50 , G11C29/00
摘要： In a semiconductor memory (1) including a memory core (2) and a logic circuit (3) which operate in synchronism with a clock signal (51), in a normal operation, a data signal (302) outputted from the memory core is latched in a latch circuit (32) provided in the logic circuit in synchronism with a rising edge of the signal which is in the same phase as that of the clock signal. In a test mode, the data signal outputted from the memory core is latched in the latch circuit in synchronism with the rising edge of the signal which is in the phase opposite to that of the clock signal. Therefore, in the test mode, if a high level width or a low level width of the clock signal is changed without changing the frequency of the clock signal, it is possible to measure a delay time on a memory data signal line from the memory core to the logic circuit without elevating the frequency of the clock signal.

65. 发明专利

DE19834415B4 未知
公开(公告)号：DE19834415B4
公开(公告)日：2005-06-30
申请号：DE19834415
申请日：1998-07-30
申请人： ELPIDA MEMORY INC
发明人： OKAMURA YOSHIFUMI
IPC分类号： G06F12/06 , G06F13/16 , G11C7/10 , G11C11/401 , G11C11/409 , G11C7/00 , G11C8/00 , G11C11/407
摘要： When a particular bank is selected the output from the data AMP of that bank is inputted and latched, and the data corresponding to the output of the data AMP is transmitted to the common data transmission line RWBUS. When the particular bank is not selected, the data on the common data transmission line RWBUS is latched to hold the final data of the previous bank during the cycle time tCK period even when the bank is switched over during the read operation, and the data on the common data transmission line RWBU can be latched, thereby enabling increased speed of the read action.

66. 发明专利

DE69733042D1 未知
公开(公告)号：DE69733042D1
公开(公告)日：2005-05-25
申请号：DE69733042
申请日：1997-06-05
申请人： ELPIDA MEMORY INC
发明人： IKEDA MINARI
IPC分类号： G11C11/409 , G11C5/02 , G11C11/401 , H01L21/8242 , H01L27/108 , G11C7/06
摘要： A semiconductor memory device includes a plurality of sense amplifiers which are divided into two groups. There are provided drive wires each extending to an associated one of the sense amplifier groups and being used to independently drive the associated group. The length of each drive wire being thereby reduced up to a half, to operated at a high speed.

67. 发明专利

DE10065785B4 未知
公开(公告)号：DE10065785B4
公开(公告)日：2005-04-21
申请号：DE10065785
申请日：2000-12-30
申请人： ELPIDA MEMORY INC
发明人： MAEDA KAZUNORI
IPC分类号： G11C7/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C7/00
摘要： A semiconductor memory device, such as a SDRAM operating in a multi-bit prefetch mode, having reduced on chip noise associated with the switching of signal lines is disclosed. According to one embodiment, the semiconductor memory device may include first and second memory cell segments (201 and 202). A first Y-address buffer decoder 100-1 can be connected to the first memory cell segment 201 and a second Y-address buffer decoder 100-2 can be connected to the second memory cell segment 202. The first Y-address decoder 100-1 receives a Y-address and a first latch signal CLK1. The second Y-address decoder 100-2 receives a Y-address and a second latch signal CLK2. A clock generating circuit 400 receives an external clock signal CLK and synchronously generates the first and second latch signals (CLK1 and CLK2). The first and second latch signals (CLK1 and CLK2) are staggered with respect to each other, so as to reduce on chip noise associated with the switching of column switch lines (YSW1 and YSW2) and I/O buses (RWBS1 and RWBS2) and the activation of associated circuitry.

68. 发明专利

DE69829039D1 未知
公开(公告)号：DE69829039D1
公开(公告)日：2005-03-24
申请号：DE69829039
申请日：1998-12-30
申请人： ELPIDA MEMORY INC
发明人： MOCHIDA YOSHIFUMI
IPC分类号： G11C11/407 , G11C7/10 , G11C7/00
摘要： A semiconductor storage device (100) having a burst mode capability for accomplishing a rapid pipeline operation is disclosed. A signal delay device (104), such as a first-in-first-out buffer (FIFO), is disposed between the data read circuitry of a memory cell array (102) and an output buffer (106). The signal delay device (104) is composed of a plurality of storage circuits (206-0 and 206-1) connected in parallel. Data values are input to selected of the storage circuits (206-0 and 206-1) by input control signals (DSEL0-DSEL1) and output from selected of the storage circuits (206-0 and 206-1) by output control signals (OSEL0-OSEL1). The DSEL0-DSEL1 and OSEL0-OSEL1 signals are generated in response to count signals (OCNT0-OCNT1).

69. 发明专利

GB2366890B Memory testing apparatus and method 未知
公开(公告)号：GB2366890B
公开(公告)日：2005-02-16
申请号：GB0110394
申请日：2001-04-27
申请人： NEC CORP , NEC ELECTRONICS CORP , ELPIDA MEMORY INC
发明人： KAWAMATA YOSUKE
IPC分类号： G01R31/28 , G06F12/16 , G11C29/44 , G11C29/56 , G11C29/00

70. 发明专利

DE102004016162A1 未知
公开(公告)号：DE102004016162A1
公开(公告)日：2004-11-11
申请号：DE102004016162
申请日：2004-03-26
申请人： ELPIDA MEMORY INC
发明人： KOYANAGI KENICHI , SAKUMA HIROSHI
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L27/108 , C23C16/06
摘要： A method for forming a capacitor insulation film includes the step of depositing a monoatomic film made of a metal by supplying a metal source including the metal and no oxygen, and depositing a metal oxide film including the metal by using a CVD technique. The method provides the metal oxide film having higher film properties with a higher throughput.

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