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61. 发明申请

US20080250271A1 Error recovery following speculative execution with an instruction processing pipeline 有权
标题翻译：使用指令处理流水线进行推测执行后出错恢复
公开(公告)号：US20080250271A1
公开(公告)日：2008-10-09
申请号：US12076165
申请日：2008-03-14
申请人： Emre Ozer , Shidhartha Das , David Michael Bull
发明人： Emre Ozer , Shidhartha Das , David Michael Bull
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F11/0721
摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.
摘要翻译：提供了指令处理流水线6。这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。错误恢复的一部分可能是从指令流水线6刷新上游程序指令。当多线程时，需要从指令流水线6清除来自包括作为错误恢复的结果而丢失的指令的线程的那些指令。还可以根据诸如特权级别，依赖指令数量等的特性来选择指令。指令流水线可以附加地/替代地设置有与这些主存储器相关联的多个信号值的多于一个的主存储元件26,28 元件26,28以交替方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获与以下程序指令相对应的信号值。这样可以避免冲洗。

62. 发明申请

US20080097713A1 Spurious signal detection 有权
标题翻译：杂散信号检测
公开(公告)号：US20080097713A1
公开(公告)日：2008-04-24
申请号：US11898923
申请日：2007-09-17
申请人： Simon Andrew Ford , David Michael Bull , Alastair David Reid
发明人： Simon Andrew Ford , David Michael Bull , Alastair David Reid
IPC分类号： G01R29/00
CPC分类号： G06F21/755
摘要： A circuit for a data processing apparatus is disclosed, said circuit comprising a data input operable to receive digital signal values, said circuit comprising: spurious signal detection logic operable to monitor a digital signal value within said circuit, and determine at least one of: a safe time window during which it is expected that said digital signal values input into said circuit may cause data transitions in said monitored digital signal value and a transition time window in which it is expected a data transition will occur; and in response to detecting either a data transition in said monitored digital signal value outside of said at least one safe time window or no data transition in said transition window, said spurious signal detection logic is operable to output a detection signal.
摘要翻译：公开了一种用于数据处理装置的电路，所述电路包括可操作以接收数字信号值的数据输入，所述电路包括：伪信号检测逻辑，可操作以监视所述电路内的数字信号值，并确定以下各项中的至少一个：安全时间窗口，期望输入到所述电路的所述数字信号值可能导致所述监视的数字信号值中的数据转换和预期将发生数据转换的转换时间窗口; 并且响应于检测到在所述至少一个安全时间窗口之外的所述监视的数字信号值中的数据转换或者在所述转换窗口中没有数据转换，所述寄生信号检测逻辑可操作以输出检测信号。

63. 发明授权

US07320091B2 Error recovery within processing stages of an integrated circuit 有权
标题翻译：集成电路处理阶段内的错误恢复
公开(公告)号：US07320091B2
公开(公告)日：2008-01-15
申请号：US11110961
申请日：2005-04-21
申请人： David T. Blaauw , David Michael Bull , Shidhartha Das
发明人： David T. Blaauw , David Michael Bull , Shidhartha Das
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F9/3861 , G06F9/3869 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024。非延迟信号捕获元件1016在非延迟捕获时间捕获来自处理逻辑1014的输出。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。误差检测电路1026和误差校正电路1028检测并校正延迟值中的随机误差，并将错误检测的延迟值提供给比较器1024。比较器1024比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获得太早，应该被错误检查的延迟值替换。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

64. 发明申请

US20070268755A1 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US20070268755A1
公开(公告)日：2007-11-22
申请号：US11436983
申请日：2006-05-19
申请人： David New , Paul Darren Hoxey , David Michael Bull , Shidhartha Das
发明人： David New , Paul Darren Hoxey , David Michael Bull , Shidhartha Das
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/12 , G11C29/1201 , G11C29/48 , G11C2207/108
摘要： A memory circuit is provided comprising a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory circuit comprises a pull-down circuit having an on configuration in which it is operable to pull-down a voltage level of at least one of the pair of conducting lines so as to affect the read operation and an off-configuration in which the pull-down circuit cannot affect the read operation. Control circuitry is provided to control whether the pull-down circuit is in the on configuration or the off configuration. The memory circuit can be incorporated in a data processing apparatus and a method of operating a memory circuit is provided in which a pull-down circuit is controlled to be in an on configuration or in an off configuration.
摘要翻译：提供了一种存储器电路，其包括存储单元，一对导线，可操作用于发信号通知存储单元的逻辑状态，读取电路可操作以通过检测至少一对导线的电压来执行读操作。存储器电路包括具有导通配置的下拉电路，其中其可操作以下拉一对导线中的至少一个导线的电压电平，以便影响读取操作，以及关断配置，其中下拉电路不能影响读操作。提供控制电路以控制下拉电路是处于接通配置还是断开配置。存储器电路可以并入数据处理设备中，并且提供了一种操作存储器电路的方法，其中下拉电路被控制为处于接通配置或断开配置。

65. 发明授权

US07263015B2 Address decoding 有权
标题翻译：地址解码
公开(公告)号：US07263015B2
公开(公告)日：2007-08-28
申请号：US11267574
申请日：2005-11-07
申请人： David Theodore Blaauw , David Michael Bull , Shidhartha Das
发明人： David Theodore Blaauw , David Michael Bull , Shidhartha Das
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/418 , G11C8/08 , G11C8/10
摘要： A signal capture element for providing a first pre-charged logic level as first and second interim address portion signals during a pre-charged period and outputting during an evaluate period an address portion logic level as the first interim address portion signal and an inverted address portion logic level as the second interim address portion signal. First and second address portion signals are derivable respectively from first and second interim address portion signals. An inverter circuit for outputting to an address decoder during a pre-charged period a second pre-charged logic level as the first and second address portion signals. The inverter circuit having transfer characteristics that maintain voltage levels such that the first and second address portion signals are interpreted to be at the second pre-charged logic level despite the first or second interim address portion signal failing to transition to a valid logic level during the evaluate period.
摘要翻译：一种信号捕捉元件，用于在预充电周期期间提供第一预充电逻辑电平作为第一和第二中间地址部分信号，并且在评估周期期间输出地址部分逻辑电平作为第一中间地址部分信号和反相地址部分逻辑电平作为第二临时地址部分信号。第一和第二地址部分信号可以分别从第一和第二临时地址部分信号导出。一种逆变器电路，用于在预充电周期期间将作为第一和第二地址部分信号的第二预充电逻辑电平输出到地址译码器。逆变器电路具有保持电压电平的传输特性，使得第一和第二地址部分信号被解释为处于第二预充电逻辑电平，尽管第一或第二临时地址部分信号在期间不能转换到有效逻辑电平评估期

66. 发明授权

US06172530B2 Decoder for generating N output signals from two or more precharged input signals 失效
标题翻译：用于从两个或多个预充电输入信号产生N个输出信号的解码器
公开(公告)号：US06172530B2
公开(公告)日：2001-01-09
申请号：US09335696
申请日：1999-06-18
申请人： David Michael Bull , Andrew Christopher Rose
发明人： David Michael Bull , Andrew Christopher Rose
IPC分类号： G11C800
CPC分类号： G11C8/00
摘要： A decoder is provided for generating N output signals, the decoder comprising a precharged gate structure arranged to receive two or more input signals and to generate N intermediate signals. In a precharge phase, the precharged gate structure is arranged to output the N intermediate signals at a first logic value, and in an evaluate phase the precharged gate structure is arranged to maintain a first intermediate signal at the first logic value, and to cause all other intermediate signals to transition to a second logic value. Further, self-timed logic is provided for receiving the N intermediate signals, and for generating the N output signals, the self-timed logic being arranged, during the precharge phase, to generate the N output signals at the second logic value, and during the evaluate phase to cause a first output signal corresponding to the first intermediate signal to transition to the first logic value. The self-timed logic is further arranged to generate each output signal from the corresponding intermediate signal as qualified to predetermined other intermediate signal, such that the transition of the first output signal to the first logic value is delayed by a first predetermined time after the predetermined other intermediate signal has transitioned to the second logic value.
摘要翻译：提供了用于产生N个输出信号的解码器，该解码器包括预充电栅极结构，其被布置为接收两个或更多个输入信号并产生N个中间信号。在预充电阶段，预充电栅极结构被布置为以第一逻辑值输出N个中间信号，并且在评估阶段中，预充电栅结构被布置成将第一中间信号保持在第一逻辑值，并且使所有其他中间信号转换到第二逻辑值。此外，提供自定时逻辑用于接收N个中间信号，并且为了产生N个输出信号，在预充电阶段期间，自定时逻辑被布置为以第二逻辑值生成N个输出信号，并且在所述评估阶段使得对应于所述第一中间信号的第一输出信号转变到所述第一逻辑值。自定时逻辑还被布置为从对应的中间信号产生符合预定的其他中间信号的每个输出信号，使得第一输出信号到第一逻辑值的转变在预定的第一预定时间后延迟第一预定时间其他中间信号已经转换到第二逻辑值。

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