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61. 发明授权

US09830153B2 Skip instruction to skip a number of instructions on a predicate 有权
公开(公告)号：US09830153B2
公开(公告)日：2017-11-28
申请号：US14311222
申请日：2014-06-20
申请人： Netronome Systems, Inc.
发明人： Gavin J. Stark
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30069 , G06F9/30072 , G06F9/30145 , G06F9/3802
摘要： A pipelined run-to-completion processor executes a conditional skip instruction. If a predicate condition as specified by a predicate code field of the skip instruction is true, then the skip instruction causes execution of a number of instructions following the skip instruction to be “skipped”. The number of instructions to be skipped is specified by a skip count field of the skip instruction. In some examples, the skip instruction includes a “flag don't touch” bit. If this bit is set, then neither the skip instruction nor any of the skipped instructions can change the values of the flags. Both the skip instruction and following instructions to be skipped are decoded one by one in sequence and pass through the processor pipeline, but the execution stage is prevented from carrying out the instruction operation of a following instruction if the predicate condition of the skip instruction was true.

62. 发明授权

US09705811B2 Simultaneous queue random early detection dropping and global random early detection dropping system 有权
公开(公告)号：US09705811B2
公开(公告)日：2017-07-11
申请号：US14507652
申请日：2014-10-06
申请人： Netronome Systems, Inc.
发明人： Ron Lamar Swartzentruber
IPC分类号： H04L12/26 , H04L12/823 , H04L12/865 , H04L12/931
CPC分类号： H04L47/326 , H04L47/6275 , H04L49/00
摘要： A method for receiving a packet descriptor associated with a packet and a queue number indicating a queue stored within a memory unit, determining a priority level of the packet and an amount of free memory available in the memory unit. Applying a global drop probability to generate a global drop indicator and applying a queue drop probability to generate a queue drop indicator. The global drop probability is a function of the amount of free memory. The queue drop probability is a function of instantaneous queue depth or drop precedence value. The packet is transmitted whenever the priority level is high. When the priority level is low, the packet is transmitted when both the global drop indicator and the queue drop indicator are a logic low value. When the priority level is low, the packet is not transmitted when either drop indicator is a logic low value.

63. 发明授权

US09699107B2 Packet engine that uses PPI addressing 有权
公开(公告)号：US09699107B2
公开(公告)日：2017-07-04
申请号：US14464690
申请日：2014-08-20
申请人： Netronome Systems, Inc.
发明人： Salma Mirza , Gavin J. Stark , Benjamin J. Cahill
IPC分类号： G06F12/10 , H04L12/863 , H04L12/935 , H04L12/861 , H04L12/801 , H04L12/747
CPC分类号： H04L47/6245 , H04L45/742 , H04L47/35 , H04L47/621 , H04L49/3072 , H04L49/9063
摘要： Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing and handling the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI (Packet Portion Identifier) Addressing Mode (PAM) in communicating with the packet engine and in instructing the packet engine to store packet portions. The packet engine uses linear memory addressing to write the packet portions into the memory, and to read the packet portions from the memory.

64. 发明授权

US09641436B1 Generating a flow ID by passing packet data serially through two CCT circuits 有权
公开(公告)号：US09641436B1
公开(公告)日：2017-05-02
申请号：US14726441
申请日：2015-05-29
申请人： Netronome Systems, Inc.
发明人： Gavin J. Stark , Stuart C. Wray
IPC分类号： H04L12/741 , H04L29/06 , H04L12/721 , H04L12/851
CPC分类号： H04L45/745 , H04L45/38 , H04L47/2441 , H04L69/22
摘要： An integrated circuit includes an input port, a first Characterize/Classify/Table Lookup and Multiplexer Circuit (CCTC), a second CCTC, and an exact-match flow table structure. The first and second CCTCs are structurally identical. The first and second CCTs are coupled together serially. In one example, an incoming packet is received onto the integrated circuit via the input port and packet information is supplied to a first characterizer of the first CCTC. Information flow passes through the classifier of the first CCT, through the Table Lookup and Multiplexer Circuit (TLMC) of the first CCT, through the characterizer of the second CCT, through the classifier of the second CCT, and out of the TLMC of the second CCT in the form of a Flow Id. The Flow Id is supplied to the exact-match flow table structure to determine whether an exact-match for the Flow Id is found in the flow table structure.

65. 发明授权

US09626306B2 Global event chain in an island-based network flow processor 有权
公开(公告)号：US09626306B2
公开(公告)日：2017-04-18
申请号：US13399983
申请日：2012-02-17
申请人： Gavin J. Stark , Jarod L. Oatley , Michael D. Secules , Ronald N. Fortino
发明人： Gavin J. Stark , Jarod L. Oatley , Michael D. Secules , Ronald N. Fortino
IPC分类号： G06F13/42 , G06F13/00 , G06F13/40
CPC分类号： G06F13/00 , G06F13/4022
摘要： An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form one or more local event rings and a global event chain. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. Each local event ring involves event ring circuits and event ring segments. In one example, an event packet being communicated along a local event ring reaches an event ring circuit. The event ring circuit examines the event packet and determines whether it meets a programmable criterion. If the event packet meets the criterion, then the event packet is inserted into the global event chain. The global event chain communicates the event packet to a global event manager that logs events and maintains statistics and other information.

66. 发明授权

US09559988B2 PPI allocation request and response for accessing a memory system 有权
标题翻译：用于访问存储系统的PPI分配请求和响应
公开(公告)号：US09559988B2
公开(公告)日：2017-01-31
申请号：US14464692
申请日：2014-08-20
申请人： Netronome Systems, Inc.
发明人： Salma Mirza , Gavin J. Stark , Ronald N. Fortino
IPC分类号： H04L12/911 , H04L12/935 , H04L12/747 , H04L12/861
CPC分类号： H04L49/3072 , H04L45/742 , H04L49/9042
摘要： Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing and handling the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI (Packet Portion Identifier) Addressing Mode (PAM) in communicating with the packet engine and in instructing the packet engine to store packet portions. A PDRSD requests a PPI from the packet engine in a PPI allocation request, and is allocated a PPI by the packet engine in a PPI allocation response, and then tags the packet portion to be written with the PPI and sends the packet portion and the PPI to the packet engine.
摘要翻译：在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。管理和处理分组部分存储到存储器中的PDRSD不是提供分组引擎。 PDRSD在与分组引擎通信并指示分组引擎存储分组部分时使用PPI（分组部分标识符）寻址模式（PAM）。 PDRSD在PPI分配请求中从分组引擎请求PPI，并且在PPI分配响应中由分组引擎分配PPI，然后标记要用PPI写入的分组部分，并发送分组部分和PPI 到包引擎。

67. 发明授权

US09548947B2 PPI de-allocate CPP bus command 有权
标题翻译： PPI取消分配CPP总线命令
公开(公告)号：US09548947B2
公开(公告)日：2017-01-17
申请号：US14464700
申请日：2014-08-20
申请人： Netronome Systems, Inc.
发明人： Salma Mirza , Gavin J. Stark , Ronald N. Fortino
IPC分类号： H04L12/935 , H04L12/863 , H04L12/947
CPC分类号： H04L49/3018 , H04L47/624 , H04L49/252
摘要： Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI addressing mode in communicating with the packet engine and in instructing the packet engine to store packet portions. A PDRSD requests a PPI from the packet engine, and is allocated a PPI by the packet engine, and then tags the packet portion to be written with the PPI and sends the packet portion and the PPI to the packet engine. Once the packet portion has been processed, a PPI de-allocation command causes the packet engine to de-allocate the PPI so that the PPI is available for allocating in association with another packet portion.
摘要翻译：在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。不是将PDRSD管理分组部分存储到存储器中，而是提供分组引擎。 PDRSD使用PPI寻址模式与分组引擎进行通信，并指示分组引擎存储分组部分。 PDRSD从分组引擎请求PPI，并由分组引擎分配PPI，然后用PPI标记要写入的分组部分，并将分组部分和PPI发送到分组引擎。一旦分组部分被处理，PPI解除分配命令使分组引擎去分配PPI，使得PPI可用于与另一分组部分相关联地分配。

68. 发明授权

US09495158B2 Multi-processor system having tripwire data merging and collision detection 有权
标题翻译：具有Tripwire数据合并和碰撞检测的多处理器系统
公开(公告)号：US09495158B2
公开(公告)日：2016-11-15
申请号：US14311217
申请日：2014-06-20
申请人： Netronome Systems, Inc.
发明人： Gavin J. Stark
IPC分类号： G06F15/00 , G06F9/30 , G06F15/82 , G06F11/36
CPC分类号： G06F9/30101 , G06F9/30003 , G06F9/30145 , G06F11/3644 , G06F11/3648 , G06F15/82
摘要： An integrated circuit includes a pool of processors and a Tripwire Data Merging and Collision Detection Circuit (TDMCDC). Each processor has a special tripwire bus port. Execution of a novel tripwire instruction causes the processor to output a tripwire value onto its tripwire bus port. Each respective tripwire bus port is coupled to a corresponding respective one of a plurality of tripwire bus inputs of the TDMCDC. The TDMCDC receives tripwire values from the processors and communicates them onto a consolidated tripwire bus. From the consolidated bus the values are communicated out of the integrated circuit and to a debug station. If more than one processor outputs a valid tripwire value at a given time, then the TDMCDC asserts a collision bit signal that is communicated along with the tripwire value. Receiving tripwire values onto the debug station facilitates use of the debug station in monitoring and debugging processor code.
摘要翻译：集成电路包括处理器池和Tripwire数据合并与冲突检测电路（TDMCDC）。每个处理器都有一个特殊的tripwire总线端口。执行新的tripwire指令使处理器将绊线值输出到其绊线总线端口上。每个相应的绊销总线端口耦合到TDMCDC的多个绊线总线输入中的对应的相应的一个。 TDMCDC从处理器接收绊线值，并将其传送到综合的绊线总线上。从整合的总线，将值从集成电路传送到调试台。如果多个处理器在给定时间输出有效的绊线值，则TDMCDC断言与绊线值一起传送的冲突位信号。将tripwire值接收到调试台便于使用调试台监视和调试处理器代码。

69. 发明授权

US09485195B2 Instantaneous random early detection packet dropping with drop precedence 有权
标题翻译：瞬时随机早期检测丢包，丢弃优先级
公开(公告)号：US09485195B2
公开(公告)日：2016-11-01
申请号：US14507602
申请日：2014-10-06
申请人： Netronome Systems, Inc.
发明人： Ron Lamar Swartzentruber , Johann H. Tönsing
IPC分类号： H04L12/931
CPC分类号： H04L49/00
摘要： A circuit that receives queue number that indicates a queue stored within a memory unit and a packet descriptor that includes a drop precedence value, and in response determines an instantaneous queue depth of the queue. The instantaneous queue depth and drop precedence value are used to determine a drop probability. The drop probability is used to randomly determine if the packet descriptor should be stored in the queue. When a packet descriptor is not stored in a queue the packet associated with the packet descriptor is dropped. The queue has a first queue depth range. A first drop probability is used when the queue depth is within the first queue depth range and the drop precedence is equal to the first value. A second drop probability is used when the queue depth is within the first queue depth range and the drop precedence equal to a second value.
摘要翻译：接收指示存储在存储器单元中的队列的队列号的电路和包括丢弃优先级值的包描述符，并且作为响应确定队列的瞬时队列深度。瞬时队列深度和丢弃优先级值用于确定丢弃概率。丢弃概率用于随机确定包描述符是否应该存储在队列中。当分组描述符不存储在队列中时，与分组描述符关联的分组被丢弃。队列具有第一个队列深度范围。当队列深度在第一队列深度范围内且丢弃优先级等于第一个值时，将使用第一个丢弃概率。当队列深度在第一队列深度范围内并且丢弃优先级等于第二值时，使用第二丢弃概率。

70. 发明授权

US09304706B2 Efficient complex network traffic management in a non-uniform memory system 有权
公开(公告)号：US09304706B2
公开(公告)日：2016-04-05
申请号：US14631784
申请日：2015-02-25
申请人： Netronome Systems, Inc.
发明人： John Anthony Harper
IPC分类号： G06F3/00 , G06F3/06 , G06F13/28 , H04L12/801
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/067 , G06F13/28 , H04L47/10 , H04L47/2441 , H04L47/621 , H04L47/6255
摘要： A network appliance includes a first processor, a second processor, a first storage device, and a second storage device. A first status information is stored in the first storage device. The first processor is coupled to the first storage device. A queue of data is stored in the second storage device. The first status information indicates if traffic data stored in the queue of data is permitted to be transmitted. The second processor is coupled to the second storage device. The first processor communicates with the second processor. The traffic data includes packet information. The first storage device is a high speed memory only accessible to the first processor. The second storage device is a high capacity memory accessible to multiple processors. The first status information is a permitted bit that indicates if the traffic data within the queue of data is permitted to be transmitted.

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