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51. 发明专利

JPS5112206B1 失效
公开(公告)号：JPS5112206B1
公开(公告)日：1976-04-17
申请号：JP6555570
申请日：1970-07-28
IPC分类号： H03M13/51 , G06F11/08 , H04L1/10

52. 发明专利

JPS5083731A 失效
公开(公告)号：JPS5083731A
公开(公告)日：1975-07-07
申请号：JP12613773
申请日：1973-11-09
IPC分类号： H02H7/05 , H03M13/51

53. 发明专利

JPS49120556A 失效
公开(公告)号：JPS49120556A
公开(公告)日：1974-11-18
申请号：JP3006973
申请日：1973-03-16
IPC分类号： H03M13/51

54. 发明申请

WO2022258386A1 METHOD AND SYSTEM FOR IDENTIFICATION VIA CHANNELS USING OPTICAL ORTHOGONAL CODES 审中-公开
公开(公告)号：WO2022258386A1
公开(公告)日：2022-12-15
申请号：PCT/EP2022/064260
申请日：2022-05-25
申请人： TECHNISCHE UNIVERSITÄT BERLIN , TECHNISCHE UNIVERSITÄT MÜNCHEN , NEW JERSEY INSTITUTE OF TECHNOLOGY
发明人： GÜNLÜ, Onur , SCHAEFER, Rafael F. , KLIEWER, Joerg , SIDORENKO, Vladimir
IPC分类号： H03M13/37 , H03M13/01 , H03M13/51 , H03M13/29 , H03M13/13
摘要： The disclosure relates to a method for identification via channels in a system having a plurality of data processing devices (10, 12, 13, 14). The method comprises selecting, in a first data processing device (10), an identifier indicative of a target second data processing device (12) of a plurality of second data processing devices (12, 13, 14); determining, in the first data processing device (10), an outer codeword from the identifier using an outer code comprising a first outer code and a second outer code; determining, in the first data processing device (10), an optical orthogonal codeword of weight W from the outer codeword using an optical orthogonal code; determining, in the first data processing device (10), a randomly selected codeword from a set of W code words of an error correction code assigned to the optical orthogonal codeword; and emitting the selected codeword from the first data processing device (10) via a channel. Further, a computer program product and a system for identification via channels are provided.

55. 发明申请

WO2016209417A1 ERROR CORRECTION USING SYNDROME MATCHING CHECKS 审中-公开
标题翻译：使用综合征匹配检查进行错误校正
公开(公告)号：WO2016209417A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/032952
申请日：2016-05-18
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： DANIEL, Andrew David
IPC分类号： H03M13/47 , H03M13/51 , H03M13/09 , H03M13/27 , H03M13/29
CPC分类号： G06F11/1004 , H03M13/096 , H03M13/27 , H03M13/29 , H03M13/2942 , H03M13/47 , H03M13/51 , H04L1/0061
摘要： A system and method are disclosed for detecting and correcting data errors based on a plurality of syndromes for a plurality of substreams common to a transmitted data stream and a received data stream. The system assigns an index value to each bit in the data stream, divides the data stream into a plurality of substreams and generates a plurality of primary codes to be transmitted including a ones code based on at least one of the number of '1' bits and '0' bits in the data stream and two or more sum codes based on the summation of index values for at least one of '1' bits and '0' bits in two or more distinct combinations of the substreams in the data stream. The generated plurality of primary codes is transmitted in association with the data stream. The system further analyzes the transmitted data stream and the transmitted plurality of primary codes as received and generates a received plurality of primary codes from the received data stream. Comparison of the transmitted and received plurality of primary codes is used to detect and correct one bit and two bit data errors in the received data stream. The determination of the erroneous bit positions in the received data stream is based on the ones code syndromes and the sum code syndromes including checking the matching of non-zero sum syndrome values.
摘要翻译：公开了一种系统和方法，用于基于用于所发送的数据流和接收的数据流公用的多个子流的多个校正子来检测和校正数据错误。系统为数据流中的每个位分配索引值，将数据流划分成多个子流，并且基于“1”位的数目中的至少一个产生要发送的多个主码，包括1个码和数据流中的“0”比特和两个或更多个和码，基于数据流中子流的两个或更多个不同组合中的“1”比特和“0”比特中的至少一个的索引值的总和。所生成的多个主代码与数据流相关联地发送。该系统进一步分析所发送的数据流和所接收的所发送的多个主码，并从接收到的数据流中生成接收到的多个主码。使用发送和接收的多个主码的比较来检测和校正接收的数据流中的一位和两位数据错误。接收到的数据流中的错误比特位置的确定是基于一个码综合征和总和码综合征，包括检查非零和校正子值的匹配。

56. 发明申请

WO2006003023A3 METHOD AND ARRANGEMENT FOR DETECTING UNIDIRECTIONAL ERRORS WITH SYSTEMATIC UNORDERED CODES 审中-公开
标题翻译：方法和系统具有体系无序码检测单向故障
公开(公告)号：WO2006003023A3
公开(公告)日：2006-04-06
申请号：PCT/EP2005007430
申请日：2005-07-06
申请人： ANSFER MBH 4TECH GES FUER TECH , TARNICK STEFFEN
发明人： TARNICK STEFFEN
IPC分类号： H03M13/49 , G06F11/10 , H03M13/51
CPC分类号： H03M13/49 , H03M13/51
摘要： The invention relates to a method and an arrangement for the detection of unidirectional errors in words of systematic unordered codes. These codes are Bose-AUED codes and Biswas-Sengupta-AUED codes. The error detection method consists in translating the code words into words of a Berger-type code which are then checked by using a method for the corresponding Berger-type code. The inventive error detection arrangement which comprises a translation circuit and a Berger-type code checker can be tested with a very low number of code words. It has the characteristic of being self-testing almost independently of the amount of code words provided and is therefore extremely suitable as embedded checker. Said checker has two outputs emitting a two-rail-signal or one output carrying a periodic signal. Moreover, this checker is not code-splitting in the conventional sense, but yet capable of detecting all unidirectional errors.
摘要翻译：本发明描述的方法和用于检测的系统的随机码字单向错误的布置。这些代码是Bose公司Aued代码和比斯瓦斯 - 森古普塔-Aued代码。该错误检测方法包括在从伯杰类型的代码字的代码字，其随后与用于相应伯杰型码的方法进行测试的翻译。用于误差检测的装置，它包括一个翻译电路和伯杰类型码检验器，可以用非常少量的码字进行测试，或达到是自测试的几乎不依赖于提供的一组码字的特性，因此是非常适合作为嵌入式检查器。这个检验器具有两个输出端，其输出端，或两轨信号的输出输出的周期性信号。此外，这种检查是不是分裂的代码来检测通常意义上的单向所有的错误，但还是能。

57. 发明专利

JP4731677B2 Method and apparatus for detecting errors in one-hot words 有权
公开(公告)号：JP4731677B2
公开(公告)日：2011-07-27
申请号：JP2000371133
申请日：2000-12-06
申请人：ヒューレット・パッカード・カンパニーHewlett−Packard Company
发明人：ケヴィン・リー・ジョーンズ , サミュエル・ディ・ナフジガー
IPC分类号： G06F11/00 , G06F11/10 , H03M13/51 , H04L1/00
CPC分类号： G06F11/1012 , H03M13/51

58. 发明专利

JP4058153B2 Encoding method and reproducing apparatus using the same 失效
公开(公告)号：JP4058153B2
公开(公告)日：2008-03-05
申请号：JP4318698
申请日：1998-02-25
申请人：株式会社日立グローバルストレージテクノロジーズ
发明人：誠一三田 , 陽一上原 , 博史井出 , 匡子塚野 , 孝奈良 , 達哉平井 , 善寿渡部 , 卓史西谷
IPC分类号： H03M13/00 , H03M13/51 , G11B20/14 , H03M5/14
CPC分类号： H03M5/145 , G11B20/1426 , G11B2020/1446

59. 发明专利

JP2005057730A Digital modulation system using orthogonal code modified to reduce autocorrelation 有权
标题翻译：数字调制系统使用正交代码修改以减少自动化
公开(公告)号：JP2005057730A
公开(公告)日：2005-03-03
申请号：JP2004168035
申请日：2004-06-07
申请人： Lucent Technol Inc , ルーセントテクノロジーズインコーポレーテッド
发明人： VAN NEE D J RICHARD
IPC分类号： H04L27/34 , H03K7/08 , H03K7/10 , H03K9/08 , H03K9/10 , H03M7/20 , H03M13/51 , H04B14/00 , H04L27/00 , H04L27/26 , H04L27/36 , H04L27/38
摘要： PROBLEM TO BE SOLVED: To provide a digital modulation system using an orthogonal code modified to reduce autocorrelation. SOLUTION: The digital modulation system uses the modified orthogonal code having reduced autocorrelation sidelobes to enhance multi-path performance and to simultaneously maintain cross-correlation property of this modified code. For example, this modified orthogonal code suppresses an autocorrelation level to a certain extent not to exceed a half length of this modified orthogonal code. In several embodiments, an M-ary orthogonal keying (MOK) system is used and this system modifies an orthogonal Walsh code by using a complementary code, thereby improving the autocorrelation property of the Walsh code. Thus, the multi-path performance of the M-ary orthogonal keying (MOK) system is enhanced and simultaneously, orthogonality of the Walsh code and the low autocorrelation property are maintained. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种使用修正为减少自相关的正交码的数字调制系统。解决方案：数字调制系统使用具有减小的自相关旁瓣的修正正交码来增强多路径性能，并同时维持该修改后的码的互相关性。例如，该修正的正交码在一定程度上抑制自相关电平不超过该修正正交码的半长度。在几个实施例中，使用M进制正交密钥（MOK）系统，并且该系统通过使用互补码修改正交沃尔什码，从而提高沃尔什码的自相关特性。因此，增强了M进制正交密钥（MOK）系统的多路径性能，同时保持了沃尔什码的正交性和低自相关特性。版权所有（C）2005，JPO＆NCIPI

60. 发明专利

JP2001111517A AIS-DETECTING CIRCUIT 失效
公开(公告)号：JP2001111517A
公开(公告)日：2001-04-20
申请号：JP28616399
申请日：1999-10-07
申请人： NIPPON ELECTRIC ENG
发明人： ONO SEIICHI
IPC分类号： H04L1/00 , H03M13/51 , H04J3/14 , H04L29/14
摘要： PROBLEM TO BE SOLVED: To provide AIS-detection with a detection threshold in an optional monitoring bit range with a comparatively small circuit and to easily change the monitoring bit range in an AIS-detecting circuit. SOLUTION: When an inputted signal 5 is at a prescribed level, load control of (m+1) frequency dividing counters 3-1, 3-2 to 3-n is performed by an n frequency dividing counter 1 to be operated by being synchronized with a clock 6 synchronized with the inputted signal 5. The m+1 frequency dividing counters 3-1, 3-2 to 3-n load an initial value 'zero' when the load control is performed, output counter expiration signals 8-1, 8-2 to 8-n, when counting is expired and stop operation. Since either one or more of the counter expiration signals 8-1, 8-2 to 80n are outputted when an AIS detecting condition is established, AIS detection is enabled by taking logical OR of each by an n input logical OR circuit 4.

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