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51. 发明申请

US20040046230A1 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 失效
公开(公告)号：US20040046230A1
公开(公告)日：2004-03-11
申请号：US10660755
申请日：2003-09-12
申请人： International Business Machines Corporation
发明人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
IPC分类号： H01L021/8242 , H01L021/20 , H01L029/00
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

52. 发明申请

US20040043560A1 Method for producing a horizontal insulation layer on a conductive material in a trench 失效
公开(公告)号：US20040043560A1
公开(公告)日：2004-03-04
申请号：US10394932
申请日：2003-03-21
发明人： Martin Popp
IPC分类号： H01L021/8242 , H01L021/20 , H01L021/31 , H01L021/469
CPC分类号： H01L21/763 , H01L21/76224 , H01L27/10861
摘要： In order to form an oxide cover on a conductive filling in a trench in a semiconductor substrate an HDP oxide is deposited on the conductive filling using a PECVD method. In this case, the layer thickness on the horizontal surface of the conductive material is greater than the layer thickness on the sidewalls of the trench. Furthermore, the layer thickness is limited in such a way that the surface of the HDP oxide within the trench has a depth with respect to the surface of the semiconductor substrate surrounding the trench, or a layer disposed thereon. In a subsequent CMP step, the HDP oxide is removed from the surrounding surface. In an isotropic etching step, the HDP oxide is removed from the sidewalls. The result is a horizontal insulation layer with a layer thickness that varies only to a slight extent over the semiconductor substrate.

53. 发明申请

US20040043556A1 Capacitor formed in a multilayer wiring structure of a semiconductor device 失效
标题翻译：在半导体器件的多层布线结构中形成的电容器
公开(公告)号：US20040043556A1
公开(公告)日：2004-03-04
申请号：US10337827
申请日：2003-01-08
申请人： MITSUBISHI DENKI KABUSHIKI KAISHA
发明人： Takashi Inbe
IPC分类号： H01L027/108 , H01L021/8242 , H01L021/20
CPC分类号： H01L28/82 , H01L21/768 , H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A capacitor which can be manufactured easily without an addition of photo masks and manufacturing processes is obtained. The capacitor has a plural via plugs (1a to 1c) which function as a first electrode and a plural via plugs (2a to 2c) which function as a second electrode. The via plugs (1a to 1c) are formed in a row along an X direction, and similarly, the via plugs (2a to 2c) are also formed in a row along the X direction. The capacitor is formed in a multilayer wiring structure of a semiconductor device, and the via plugs (1a to 1c) and the via plugs (2a to 2c) face each other with part of an interlayer insulating film between. Part of the interlayer insulating film which is put between the via plugs (1a to 1c) and the via plugs (2a to 2c) function as a capacitor dielectric film.
摘要翻译：获得可以容易地制造而不添加光掩模和制造工艺的电容器。该电容器具有作为第一电极的多个通孔插头（1a〜1c）和充当第二电极的多个通孔塞（2a〜2c）。通孔塞（1a〜1c）沿着X方向成一行，同样地，通孔塞（2a〜2c）也沿X方向成一行。电容器形成在半导体器件的多层布线结构中，并且通孔塞（1a至1c）和通孔塞（2a至2c）彼此面对，其间具有层间绝缘膜的一部分。放置在通孔（1a〜1c）和通孔塞（2a〜2c）之间的层间绝缘膜的一部分用作电容器电介质膜。

54. 发明申请

US20040041194A1 Metal plating using seed film 失效
标题翻译：使用种子膜进行金属电镀
公开(公告)号：US20040041194A1
公开(公告)日：2004-03-04
申请号：US10231435
申请日：2002-08-29
申请人： MICRON TECHNOLOGY, INC.
发明人： Eugene P. Marsh
IPC分类号： H01L021/20
CPC分类号： C23C16/0281 , C23C16/045 , C23C16/16 , C23C16/18 , C23C16/24 , C23C16/30 , C23C16/45525 , C23C16/45529 , C23C16/56 , C25D5/02 , C25D7/123 , H01L21/28562 , H01L21/288 , H01L21/2885 , H01L21/32051 , H01L21/4846 , H01L21/76846 , H01L21/76873 , H01L23/5223 , H01L27/0805 , H01L28/90 , H01L2924/0002 , Y10T428/12542 , Y10T428/12611 , Y10T428/12861 , Y10T428/12868 , Y10T428/12875 , Y10T428/265 , H01L2924/00
摘要： A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each layer of the one or more noble metal layers is no greater than a monolayer. The seed film also includes either one or more conductive metal oxide layers or one or more silicon oxide layers, where either layer is no greater than a monolayer. The seed film can be used in plating, including electroplating, conductive layers, over at least a portion of the seed film. Conductive layers formed with the seed film can be used in fabricating an integrated circuit, including fabricating capacitor structures in the integrated circuit.
摘要翻译：提供种子膜和将种子膜并入半导体应用中的方法。种子膜包括一个或多个贵金属层，其中所述一个或多个贵金属层的每层不大于单层。种子膜还包括一个或多个导电金属氧化物层或一个或多个氧化硅层，其中任一层不大于单层。种子膜可用于电镀，包括电镀，导电层，至少部分种子膜。用种子膜形成的导电层可用于制造集成电路，包括在集成电路中制造电容器结构。

55. 发明申请

US20040038502A1 Method of detecting chemical mechanical polishing endpoints in thin film head processes 审中-公开
标题翻译：在薄膜头工艺中检测化学机械抛光终点的方法
公开(公告)号：US20040038502A1
公开(公告)日：2004-02-26
申请号：US10603389
申请日：2003-06-25
发明人： Sethuraman Jayashankar , Earl C. Johns
IPC分类号： H01L021/20
CPC分类号： B24B37/013 , B24B49/04 , B24B49/12
摘要： A method of chemical mechanical polishing a wafer comprises: forming an optical property modifying layer on a surface of a feature of interest disposed on a wafer, removing material from the wafer using a chemical mechanical polishing process, directing light onto a surface of the wafer and using light reflected from a surface of the wafer to determine when the optical property modifying layer has been reached, and stopping the chemical mechanical polishing process in response to the determination that the optical property modifying layer has been reached. A wafer for use in manufacturing a magnetic recording head is also included. The wafer comprises a substrate, a pattern including an optical property modifying layer on a surface of a feature of interest supported by the substrate, and a dielectric layer positioned on the optical property modifying layer.
摘要翻译：化学机械抛光晶片的方法包括：在感兴趣特征的表面上形成光学性质改性层，设置在晶片上，使用化学机械抛光工艺从晶片去除材料，将光引导到晶片的表面上;以及使用从晶片的表面反射的光确定何时已经到达光学性质改性层，并且响应于已经达到光学性质改性层的确定停止化学机械抛光工艺。还包括用于制造磁记录头的晶片。晶片包括基板，包括由基板支撑的感兴趣特征的表面上的光学性质改性层的图案，以及位于光学性质改性层上的介电层。

56. 发明申请

US20040038500A1 Thin microelectronic substrates and methods of manufacture 失效
公开(公告)号：US20040038500A1
公开(公告)日：2004-02-26
申请号：US10646608
申请日：2003-08-21
发明人： Charles E. Larson , Timothy E. Murphy , Bryan L. Taylor , Jon M. Long , Mark W. Ellis , Vincent L. Riley
IPC分类号： H01L021/20
CPC分类号： H01L21/6835 , H01L21/67092 , H01L21/6838 , H01L21/76251 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2924/0002 , Y10S438/94 , Y10S438/977 , H01L2924/00
摘要： A microelectronic substrate and method for manufacture. In one embodiment, the microelectronic substrate includes a body having a first surface, a second surface facing a direction opposite from the first surface, and a plurality of voids in the body between the first and second surfaces. The voids can extend from the first surface to a separation region beneath the first surface. At least one operable microelectronic device is formed at and/or proximate to the first surface of the substrate material, and then a first stratum of the microelectronic substrate above the separation region is separated from a second stratum of the microelectronic substrate below the separation region. The first stratum of the microelectronic substrate can be further separated into discrete microelectronic dies before the first stratum is separated from the second stratum. In one aspect of this embodiment, the substrate can support a film and microelectronic devices can be formed in the film and/or in the substrate.

57. 发明申请

US20040038491A1 Capacitor for semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件用电容器及其制造方法
公开(公告)号：US20040038491A1
公开(公告)日：2004-02-26
申请号：US10635025
申请日：2003-08-06
申请人： Hynix Semiconductor, Inc.
发明人： Won Cheol Cho
IPC分类号： H01L021/20
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10852 , H01L28/86
摘要： A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.
摘要翻译：公开了一种用于半导体器件的电容器，其通过简化的制造工艺产生增加的电容。电容器具有形成在其上形成有杂质区域的半导体器件上的存储节点电极结构。存储节点电极结构包括形成在由半导体器件限定的存储节点孔中的掩埋层，所述掩埋层与至少一个杂质区相接触，所述掩埋层形成在所述掩埋层上并延伸超过所述掩埋层，第一圆柱形电极具有从底层向上延伸的第一壁，以及第二圆柱形电极，其具有从底层向上延伸并设置在第一圆柱形电极的外侧上的第二壁。

58. 发明申请

US20040018692A1 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20040018692A1
公开(公告)日：2004-01-29
申请号：US10620613
申请日：2003-07-17
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Teruhito Ohnishi , Takeshi Takagi , Akira Asai , Taizo Fujii , Mitsuo Sugiura , Yoshihisa Minami
IPC分类号： H01L021/20 , H01L029/93
CPC分类号： H01L29/93 , H01L27/0664 , H01L27/0808
摘要： A variable capacitor includes an Nnull layer including a variable capacitance region, a Pnull layer epitaxially grown on the Nnull layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the Nnull layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the Pnull layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the Nnull layer, reduction in variation range of the capacitance can be suppressed.
摘要翻译：可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层的可变电容器。由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

59. 发明申请

US20040018679A1 Storage electrode of a semiconductor memory device and method for fabricating the same 有权
标题翻译：半导体存储器件的存储电极及其制造方法
公开(公告)号：US20040018679A1
公开(公告)日：2004-01-29
申请号：US10418090
申请日：2003-04-18
发明人： Young Sub Yu , Seok Sik Kim , Ki Hyun Hwang , Han Jin Lim , Sung Je Choi
IPC分类号： H01L021/44 , H01L021/8242 , H01L021/20
CPC分类号： H01L28/91 , H01L27/10814 , H01L27/10855
摘要： A storage electrode has a truncated-conical nullpipe-shapednull top section having a small inner diameter, mounted on a cylindrical base section having a large inner diameter. To fabricate the storage electrode, a buried contact plug is formed on a first insulating layer on a wafer, and an etching stop layer and a second insulating layer are formed on the first insulating layer. A third insulating layer is formed on the second insulating layer after implanting impurities into the second insulating layer. An opening is formed by anisotropically etching the third insulating layer and the second insulating layer using a photoresist pattern as an etching mask. A cleaning process is carried out such that the second insulating layer exposed through the opening is isotropically etched. After depositing polysilicon along a profile of the second and third insulating layers to a uniform thickness, the remaining third and second insulating layers are removed.
摘要翻译：存储电极具有安装在具有大内径的圆筒形基部上的具有小内径的截头圆锥形“管状”顶部部分。为了制造存储电极，在晶片上的第一绝缘层上形成掩埋接触插塞，在第一绝缘层上形成蚀刻停止层和第二绝缘层。在将杂质注入第二绝缘层之后，在第二绝缘层上形成第三绝缘层。通过使用光致抗蚀剂图案作为蚀刻掩模对第三绝缘层和第二绝缘层进行各向异性蚀刻来形成开口。进行清洁处理，使得通过开口暴露的第二绝缘层被各向同性地蚀刻。沿着第二和第三绝缘层的轮廓将多晶硅沉积到均匀的厚度之后，剩余的第三和第二绝缘层被去除。

60. 发明申请

US20040014295A1 Atomic layer deposition of titanium nitride using batch type chamber and method for fabricating capacitor by using the same 失效
标题翻译：使用分批式室的氮化钛的原子层沉积及其使用制造电容器的方法
公开(公告)号：US20040014295A1
公开(公告)日：2004-01-22
申请号：US10615038
申请日：2003-07-08
申请人： HYNIX SEMICONDUCTOR INC.
发明人： Young-Soo Kim
IPC分类号： H01L021/20
CPC分类号： C23C16/45527 , C23C16/34 , H01L21/28562 , H01L28/75
摘要： The present invention relates to a method for fabricating a capacitor employing ALD-TiN as an upper electrode and being suitable for preventing a deterioration of a leakage current property which uses an ALD-TiN as an upper electrode. The method for fabricating the capacitor includes: forming a lower electrode on a semiconductor substrate; forming a dielectric layer on the lower electrode; loading the semiconductor substrate containing the dielectric layer into a deposition chamber; nitriding a surface of the dielectric layer while NH3 gas is flowed into the deposition chamber; and forming an upper layer by using a source gas NH3, containing Titanium (Ti) on the nitrated surface of the dielectric layer through an atomic layer deposition (ALD) method.
摘要翻译：本发明涉及一种制造使用ALD-TiN作为上电极的电容器的方法，并且适用于防止使用ALD-TiN作为上电极的泄漏电流特性的劣化。制造电容器的方法包括：在半导体衬底上形成下电极; 在下电极上形成电介质层; 将包含电介质层的半导体衬底加载到沉积室中; 在NH 3气体流入沉积室的过程中氮化电介质层的表面; 并通过使用原子层沉积（ALD）方法在电介质层的硝化表面上使用含有钛（Ti）的源气体NH 3形成上层。

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